参数资料
型号: PCA9698DGG,512
厂商: NXP Semiconductors
文件页数: 38/48页
文件大小: 0K
描述: IC I/O EXPANDER I2C 40B 56TSSOP
产品培训模块: I²C Bus Fundamentals
特色产品: NXP - I2C Interface
标准包装: 35
接口: I²C
输入/输出数: 40
中断输出:
频率 - 时钟: 1MHz
电源电压: 2.3 V ~ 5.5 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 56-TFSOP(0.240",6.10mm 宽)
供应商设备封装: 56-TSSOP
包装: 管件
包括: POR
产品目录页面: 826 (CN2011-ZH PDF)
其它名称: 568-3241-5
935278614512
PCA9698DGG
43
7810C–AVR–10/12
Atmel ATmega328P [Preliminary]
The BODS bit is active three clock cycles after it is set. A sleep instruction must be executed
while BODS is active in order to turn off the BOD for the actual sleep mode. The BODS bit is
automatically cleared after three clock cycles.
Bit 5 – BODSE: BOD Sleep Enable
BODSE enables setting of BODS control bit, as explained in BODS bit description. BOD disable
is controlled by a timed sequence.
9.11.3
PRR – Power Reduction Register
Bit 7 - PRTWI: Power Reduction TWI
Writing a logic one to this bit shuts down the TWI by stopping the clock to the module. When
waking up the TWI again, the TWI should be re initialized to ensure proper operation.
Bit 6 - PRTIM2: Power Reduction Timer/Counter2
Writing a logic one to this bit shuts down the Timer/Counter2 module in synchronous mode (AS2
is 0). When the Timer/Counter2 is enabled, operation will continue like before the shutdown.
Bit 5 - PRTIM0: Power Reduction Timer/Counter0
Writing a logic one to this bit shuts down the Timer/Counter0 module. When the Timer/Counter0
is enabled, operation will continue like before the shutdown.
Bit 4 - Res: Reserved bit
This bit is reserved in ATmega328P and will always read as zero.
Bit 3 - PRTIM1: Power Reduction Timer/Counter1
Writing a logic one to this bit shuts down the Timer/Counter1 module. When the Timer/Counter1
is enabled, operation will continue like before the shutdown.
Bit 2 - PRSPI: Power Reduction Serial Peripheral Interface
If using debugWIRE On-chip Debug System, this bit should not be written to one.
Writing a logic one to this bit shuts down the Serial Peripheral Interface by stopping the clock to
the module. When waking up the SPI again, the SPI should be re initialized to ensure proper
operation.
Bit 1 - PRUSART0: Power Reduction USART0
Writing a logic one to this bit shuts down the USART by stopping the clock to the module. When
waking up the USART again, the USART should be re initialized to ensure proper operation.
Bit 0 - PRADC: Power Reduction ADC
Writing a logic one to this bit shuts down the ADC. The ADC must be disabled before shut down.
The analog comparator cannot use the ADC input MUX when the ADC is shut down.
Bit
7
6
543
2
1
0
PRTWI
PRTIM2
PRTIM0
PRTIM1
PRSPI
PRUSART0
PRADC
PRR
Read/Write
R/W
R
R/W
Initial Value
0
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