参数资料
型号: PCA9698DGG,512
厂商: NXP Semiconductors
文件页数: 5/48页
文件大小: 0K
描述: IC I/O EXPANDER I2C 40B 56TSSOP
产品培训模块: I²C Bus Fundamentals
特色产品: NXP - I2C Interface
标准包装: 35
接口: I²C
输入/输出数: 40
中断输出:
频率 - 时钟: 1MHz
电源电压: 2.3 V ~ 5.5 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 56-TFSOP(0.240",6.10mm 宽)
供应商设备封装: 56-TSSOP
包装: 管件
包括: POR
产品目录页面: 826 (CN2011-ZH PDF)
其它名称: 568-3241-5
935278614512
PCA9698DGG
13
7810C–AVR–10/12
Atmel ATmega328P [Preliminary]
6.5.1
SPH and SPL – Stack Pointer High and Stack Pointer Low Register
6.6
Instruction Execution Timing
This section describes the general access timing concepts for instruction execution. The AVR
CPU is driven by the CPU clock clk
CPU, directly generated from the selected clock source for the
chip. No internal clock division is used.
Figure 6-4 shows the parallel instruction fetches and instruction executions enabled by the Har-
vard architecture and the fast-access Register File concept. This is the basic pipelining concept
to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost,
functions per clocks, and functions per power-unit.
Figure 6-4.
The Parallel Instruction Fetches and Instruction Executions
Figure 6-5 shows the internal timing concept for the Register File. In a single clock cycle an ALU
operation using two register operands is executed, and the result is stored back to the destina-
tion register.
Figure 6-5.
Single Cycle ALU Operation
Bit
151413121110
9
8
SP15
SP14
SP13
SP12
SP11
SP10
SP9
SP8
SPH
SP7
SP6
SP5
SP4
SP3
SP2
SP1
SP0
SPL
76543210
Read/Write
R/W
Initial Value
RAMEND
clk
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
T1
T2
T3
T4
CPU
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
T1
T2
T3
T4
clk
CPU
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