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| 型号： | PCA9698DGG,512 |
| 厂商： | NXP Semiconductors |
| 文件页数： | 6/48页 |
| 文件大小： | 0K |
| 描述： | IC I/O EXPANDER I2C 40B 56TSSOP |
| 产品培训模块： | I²C Bus Fundamentals |
| 特色产品： | NXP - I2C Interface |
| 标准包装： | 35 |
| 接口： | I²C |
| 输入/输出数： | 40 |
| 中断输出： | 是 |
| 频率 - 时钟： | 1MHz |
| 电源电压： | 2.3 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 56-TFSOP（0.240"，6.10mm 宽） |
| 供应商设备封装： | 56-TSSOP |
| 包装： | 管件 |
| 包括： | POR |
| 产品目录页面： | 826 (CN2011-ZH PDF) |
| 其它名称： | 568-3241-5 935278614512 PCA9698DGG |
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14
7810C–AVR–10/12
Atmel ATmega328P [Preliminary]
6.7
Reset and Interrupt Handling
The AVR provides several different interrupt sources. These interrupts and the separate Reset
Vector each have a separate program vector in the program memory space. All interrupts are
assigned individual enable bits which must be written logic one together with the Global Interrupt
Enable bit in the Status Register in order to enable the interrupt. Depending on the Program
Counter value, interrupts may be automatically disabled when Boot Lock bits BLB02 or BLB12
are programmed. This feature improves software security. See the section “Memory Program-
ming” on page 286 for details.
The lowest addresses in the program memory space are by default defined as the Reset and
Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 56. The list also
determines the priority levels of the different interrupts. The lower the address the higher is the
priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request
0. The Interrupt Vectors can be moved to the start of the Boot Flash section by setting the IVSEL
bit in the MCU Control Register (MCUCR). Refer to “Interrupts” on page 56 for more information.
The Reset Vector can also be moved to the start of the Boot Flash section by programming the
BOOTRST Fuse, see “Boot Loader Support – Read-While-Write Self-Programming” on page
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are dis-
abled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled
interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a
Return from Interrupt instruction – RETI – is executed.
There are basically two types of interrupts. The first type is triggered by an event that sets the
Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vec-
tor in order to execute the interrupt handling routine, and hardware clears the corresponding
Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s)
to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is
cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is
cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt
Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the
Global Interrupt Enable bit is set, and will then be executed by order of priority.
The second type of interrupts will trigger as long as the interrupt condition is present. These
interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the
interrupt is enabled, the interrupt will not be triggered.
When the AVR exits from an interrupt, it will always return to the main program and execute one
more instruction before any pending interrupt is served.
Note that the Status Register is not automatically stored when entering an interrupt routine, nor
restored when returning from an interrupt routine. This must be handled by software.
When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled.
No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the
CLI instruction. The following example shows how this can be used to avoid interrupts during the
timed EEPROM write sequence.
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相关代理商/技术参数 |
参数描述 |
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| PCA9698DGGS911,51 | 功能描述:I2C 接口集成电路 40-bit Fm I2C Bus I/O port w/Reset RoHS:否 制造商:NXP Semiconductors 电源电压-最大:5.5 V 电源电压-最小:2.3 V 最大工作频率:400 KHz 最大工作温度:+ 85 C 封装 / 箱体:TSSOP-16 |
| PCA9698DGGT | 制造商:NXP Semiconductors 功能描述:I2C GPIO Expander 5.5V 56-Pin TSSOP T/R |
| PCA9698DGG-T | 制造商:NXP Semiconductors 功能描述:I2C GPIO Expander 5.5V 56-Pin TSSOP T/R |
| PCA96PWS911,118 | 功能描述:接口-I/O扩展器 8-BIT I2C FM QB RoHS:否 制造商:NXP Semiconductors 逻辑系列: 输入/输出端数量: 最大工作频率:100 kHz 工作电源电压:1.65 V to 5.5 V 工作温度范围:- 40 C to + 85 C 安装风格:SMD/SMT 封装 / 箱体:HVQFN-16 封装:Reel |
| PCA9701D | 功能描述:寄存器 16BIT SPI 18V GPI INT -40 +125 RoHS:否 制造商:NXP Semiconductors 逻辑类型:CMOS 逻辑系列:HC 电路数量:1 最大时钟频率:36 MHz 传播延迟时间: 高电平输出电流:- 7.8 mA 低电平输出电流:7.8 mA 电源电压-最大:6 V 最大工作温度:+ 125 C 封装 / 箱体:SOT-38 封装:Tube |
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