参数资料
型号: PI7C8150BNDIE
厂商: Pericom
文件页数: 101/109页
文件大小: 0K
描述: IC PCI-PCI BRIDGE ASYNC 256-PBGA
标准包装: 90
系列: *
应用: *
接口: *
电源电压: *
封装/外壳: 256-BGA
供应商设备封装: 256-PBGA(17x17)
包装: 管件
安装类型: 表面贴装
PI7C8150B
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 91 of 109
April 2009 – Revision 1.08
14.1.41
P_SERR_L STATUS REGISTER – OFFSET 68h
Bit
Function
Type
Description
16
Address Parity
Error
R/WC
1: Signal P_SERR_L was asserted because an address parity error
was detected on P or S bus.
Reset to 0
17
Posted Write
Data Parity Error
R/WC
1: Signal P_SERR_L was asserted because a posted write data parity
error was detected on the target bus.
Reset to 0
18
Posted Write
Non-delivery
R/WC
1: Signal P_SERR_L was asserted because the bridge was unable to
deliver post memory write data to the target after 2
24 attempts.
Reset to 0
19
Target Abort
during Posted
Write
R/WC
1: Signal P_SERR_L was asserted because the bridge received a
target abort when delivering post memory write data.
Reset to 0.
20
Master Abort
during Posted
Write
R/WC
1: Signal P_SERR_L was asserted because the bridge received a
master abort when attempting to deliver post memory write data
Reset to 0.
21
Delayed Write
Non-delivery
R/WC
1: Signal P_SERR_L was asserted because the bridge was unable to
deliver delayed write data after 2
24 attempts.
Reset to 0
22
Delayed Read –
No Data from
Target
R/WC
1: Signal P_SERR_L was asserted because the bridge was unable to
read any data from the target after 2
24 attempts.
Reset to 0.
23
Delayed
Transaction
Master Timeout
R/WC
1: Signal P_SERR_L was asserted because a master did not repeat a
read or write transaction before master timeout.
Reset to 0.
14.1.42
PORT OPTION REGISTER – OFFSET 74h
Bit
Function
Type
Description
0
Reserved
R/O
Reserved. Returns 0 when read. Reset to 0.
1
Primary MEMR
Command Alias
Enable
R/W
Controls PI7C8150B’s detection mechanism for matching memory
read retry cycles from the initiator on the primary interface
0: exact matching for non-posted memory write retry cycles from
initiator on the primary interface
1: alias MEMRL or MEMRM to MEMR for memory read retry
cycles from the initiator on the primary interface
Reset to 0
2
Primary MEMW
Command Alias
Enable
R/W
Controls PI7C8150B’s detection mechanism for matching non-posted
memory write retry cycles from the initiator on the primary interface
0: exact matching for non-posted memory write retry cycles from
initiator on the primary interface
1: alias MEMWI to MEMW for non-posted memory write retry
cycles from initiator on the primary interface
Reset to 0
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