参数资料
型号: PI7C8150BNDIE
厂商: Pericom
文件页数: 81/109页
文件大小: 0K
描述: IC PCI-PCI BRIDGE ASYNC 256-PBGA
标准包装: 90
系列: *
应用: *
接口: *
电源电压: *
封装/外壳: 256-BGA
供应商设备封装: 256-PBGA(17x17)
包装: 管件
安装类型: 表面贴装
PI7C8150B
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 73 of 109
April 2009 – Revision 1.08
When S_RESET_L is asserted by means of the secondary reset bit, PI7C8150B remains
accessible during secondary interface reset and continues to respond to accesses to its
configuration space from the primary interface.
12.3
CHIP RESET
The chip reset bit in the diagnostic control register can be used to reset the PI7C8150B and
the secondary bus.
When the chip reset bit is set, all registers and chip state are reset and all signals are
tristated. S_RESET_L is asserted and the secondary reset bit is automatically set.
S_RESET_L remains asserted until a configuration write operation clears the secondary
reset bit and the serial clock mask has been shifted in. Within 20 PCI clock cycles after
completion of the configuration write operation, PI7C8150B’s reset bit automatically clears
and PI7C8150B is ready for configuration.
During reset, PI7C8150B is inaccessible.
13
SUPPORTED COMMANDS
The PCI command set is given below for the primary and secondary interfaces.
13.1
PRIMARY INTERFACE
P_CBE [3:0]
Command
Action
0000
Interrupt
Acknowledge
Ignore
0001
Special Cycle
Do not claim. Ignore.
0010
I/O Read
1. If address is within pass through I/O range, claim and pass
through.
2. Otherwise, do not pass through and do not claim for
internal access.
0011
I/O Write
Same as I/O Read.
0100
Reserved
-----
0101
Reserved
-----
0110
Memory Read
1. If address is within pass through memory range, claim and
pass through.
2. If address is within pass through memory mapped I/O
range, claim and pass through.
3. Otherwise, do not pass through and do not claim for
internal access.
0111
Memory Write
Same as Memory Read.
1000
Reserved
-----
1001
Reserved
-----
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