参数资料
| 型号： | PI7C8150BNDIE |
| 厂商： | Pericom |
| 文件页数： | 62/109页 |
| 文件大小： | 0K |
| 描述： | IC PCI-PCI BRIDGE ASYNC 256-PBGA |
| 标准包装： | 90 |
| 系列： | * |
| 应用： | * |
| 接口： | * |
| 电源电压： | * |
| 封装/外壳： | 256-BGA |
| 供应商设备封装： | 256-PBGA（17x17） |
| 包装： | 管件 |
| 安装类型： | 表面贴装 |
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PI7C8150B
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 56 of 109
April 2009 – Revision 1.08
PI7C8150B has not detected the parity error on the primary (initiator) bus
which the parity error is not forwarded from the primary bus to the
secondary bus.
During upstream write transactions, when a data parity error is reported on the target
(primary) bus by the target’s assertion of P_PERR_L, the following events occur:
PI7C8150B sets the data parity detected bit in the status register, if the parity error
response bit is set in the command register of the primary interface.
PI7C8150B asserts P_SERR_L and sets the signaled system error bit in the status
register, if all the following conditions are met:
The SERR_L enable bit is set in the command register.
The parity error response bit is set in the bridge control register of the
secondary interface.
The parity error response bit is set in the command register of the primary
interface.
PI7C8150B has not detected the parity error on the secondary (initiator)
bus, which the parity error is not forwarded from the secondary bus to the
primary bus.
Assertion of P_SERR_L is used to signal the parity error condition when the initiator does
not know that the error occurred. Because the data has already been delivered with no
errors, there is no other way to signal this information back to the initiator. If the parity
error has forwarded from the initiating bus to the target bus, P_SERR_L will not be
asserted.
6.3
DATA PARITY ERROR REPORTING SUMMARY
In the previous sections, the responses of PI7C8150B to data parity errors are presented
according to the type of transaction in progress. This section organizes the responses of
PI7C8150B to data parity errors according to the status bits that PI7C8150B sets and the
signals that it asserts. Table 6-1 shows setting the detected parity error bit in the status
register, corresponding to the primary interface. This bit is set when PI7C8150B detects a
parity error on the primary interface.
Table 6-1. Setting the Primary Interface Detected Parity Error Bit
Primary Detected
Parity Error Bit
Transaction Type
Direction
Bus Where Error
Was Detected
Primary/
Secondary Parity
Error Response
Bits
0
Read
Downstream
Primary
x / x
0
Read
Downstream
Secondary
x / x
1
Read
Upstream
Primary
x / x
0
Read
Upstream
Secondary
x / x
1
Posted Write
Downstream
Primary
x / x
0
Posted Write
Downstream
Secondary
x / x
0
Posted Write
Upstream
Primary
x / x
0
Posted Write
Upstream
Secondary
x / x
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相关代理商/技术参数 |
参数描述 |
|---|---|
| PI7C8150BNDIE-33 | 功能描述:外围驱动器与原件 - PCI 2 Port 32B PCI Bridge RoHS:否 制造商:PLX Technology 工作电源电压: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:FCBGA-1156 封装:Tray |
| PI7C8150DMAE | 功能描述:外围驱动器与原件 - PCI 2-Port PCI Bridge RoHS:否 制造商:PLX Technology 工作电源电压: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:FCBGA-1156 封装:Tray |
| PI7C8150DND | 制造商:Pericom Semiconductor Corporation 功能描述:BRIDGE 制造商:Pericom Semiconductor Corporation 功能描述:2 PORT PCI BRIDGE - Rail/Tube |
| PI7C8150DNDE | 功能描述:外围驱动器与原件 - PCI 2-Port PCI Bridge RoHS:否 制造商:PLX Technology 工作电源电压: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:FCBGA-1156 封装:Tray |
| PI7C8150EVB | 功能描述:界面开发工具 2 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 产品:Evaluation Boards 类型:RS-485 工具用于评估:ADM3485E 接口类型:RS-485 工作电源电压:3.3 V |
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