参数资料
型号: PI7C8150BNDIE
厂商: Pericom
文件页数: 102/109页
文件大小: 0K
描述: IC PCI-PCI BRIDGE ASYNC 256-PBGA
标准包装: 90
系列: *
应用: *
接口: *
电源电压: *
封装/外壳: 256-BGA
供应商设备封装: 256-PBGA(17x17)
包装: 管件
安装类型: 表面贴装
PI7C8150B
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 92 of 109
April 2009 – Revision 1.08
Bit
Function
Type
Description
3
Secondary
MEMR
Command Alias
Enable
R/W
Controls PI7C8150B’s detection mechanism for matching memory
read retry cycles from the initiator on the secondary
0: exact matching for memory read retry cycles from initiator on the
secondary interface
1: alias MEMRL or MEMRM to MEMR for memory read retry
cycles from initiator on the secondary interface
Reset to 0
4
Secondary
MEMW
Command Alias
Enable
R/W
Controls PI7C8150B’s detection mechanism for matching non-posted
memory write retry cycles from the initiator on the primary interface
0: exact matching for non-posted memory write retry cycles from
initiator on the secondary interface
1: alias MEMWI to MEMW for non-posted memory write retry
cycles from initiator on the secondary interface
Reset to 0
5:6
Reserved
R/O
Reserved. Returns 0 when read. Reset to 0.
7
Primary
MEMWI
Command Alias
Enable
R/W
Controls PI7C8150B’s detection mechanism for matching non-posted
memory write and invalidate cycles from the initiator on the primary
interface
0: When accepting MEMWI command at the primary interface,
PI7C8150B converts MEMWI to MEMW command on the
secondary interface
1: Disconnects MEMWI command at aligned cache line boundaries
8
Secondary
MEMWI
Command Alias
Enable
R/W
Controls PI7C8150B’s detection mechanism for matching non-posted
memory write and invalidate cycles from the initiator on the
secondary interface
0: When accepting MEMWI command at the secondary interface,
PI7C8150B converts MEMWI to MEMW command on the primary
interface
1: Disconnects MEMWI command at aligned cache line boundaries
9
Enable Long
Request
R/W
Controls PI7C8150B’s ability to enable long requests for lock cycles
0: normal lock operation
1: enable long request for lock cycle
Reset to 0
10
Enable
Secondary To
Hold Request
Longer
R/W
Control’s PI7C8150B’s ability to enable the secondary bus to hold
requests longer.
0: internal secondary master will release REQ_L after FRAME_L
assertion
1: internal secondary master will hold REQ_L until there is no
transactions pending in FIFO or until terminated by target
Reset to 1
11
Enable Primary
To Hold Request
Longer
R/W
Control’s PI7C8150B’s ability to hold requests longer at the Primary
Port.
0: internal Primary master will release REQ_L after FRAME_L
assertion
1: internal Primary master will hold REQ_L until there is no
transactions pending in FIFO or until terminated by target
Reset to 1
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