参数资料
| 型号： | PI7C8150BNDIE |
| 厂商： | Pericom |
| 文件页数： | 76/109页 |
| 文件大小： | 0K |
| 描述： | IC PCI-PCI BRIDGE ASYNC 256-PBGA |
| 标准包装： | 90 |
| 系列： | * |
| 应用： | * |
| 接口： | * |
| 电源电压： | * |
| 封装/外壳： | 256-BGA |
| 供应商设备封装： | 256-PBGA（17x17） |
| 包装： | 管件 |
| 安装类型： | 表面贴装 |
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PI7C8150B
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 69 of 109
April 2009 – Revision 1.08
Input data field
The bottom four bits of the output enable fields control whether each GPIO signal is input
only or bi-directional. Each signal is controlled independently by a bit in each output
enable control field. If a 1 is written to the write-1-to-set field, the corresponding pin is
activated as an output. If a 1 is written to the write-1-to-clear field, the output driver is tri-
stated, and the pin is then input only. Writing zeroes to these registers has no effect. The
reset for these signals is input only.
The input data field is read only and reflects the current value of the GPIO pins. A type 0
configuration read operation to this address is used to obtain the values of these pins. All
pins can be read at any time, whether configured as input only or as bi-directional.
The output data fields also use the write-1-to-set and write-1-to-clear mode. If a 1 is
written to the write-1-to-set field and the pin is enabled as an output, the corresponding
GPIO output is driven HIGH. If a 1 is written to the write-1-to-clear field and the pin is
enabled as an output, the corresponding GPIO output is driven LOW. Writing zeros to
these registers has no effect. The value written to the output register will be driven only
when the GPIO signal is configured as bi-directional. A type 0 configuration write
operation is used to program these fields. The rest value for the output is 0.
10.2
SECONDARY CLOCK CONTROL
The PI7C8150B uses the GPIO pins and the MSK_IN signal to input a 16-bit serial data
stream. This data stream is shifted into the secondary clock control register and is used for
selectively disabling secondary clock outputs.
The serial data stream is shifted in as soon as P_RST_L is detected deasserted and the
secondary reset signal, S_RST_L, is detected asserted. The deassertion of S_RST_L is
delayed until the PI7C8150B completes shifting in the clock mask data, which takes 23
clock cycles. After that, the GPIO pins can be used as general-purpose I/O pins.
An external shift register should be used to load and shift the data. The GPIO pins are used
for shift register control and serial data input. Table 10-1 shows the operation of the GPIO
pins.
Table 10-1. GPIO Operation
GPIO Pin
Operation
GPIO[0]
Shift register clock output at 33MHz max frequency
GPIO[1]
Not used
GPIO[2]
Shift register control
0: Load
1: Shift
GPIO[3]
Not used
The data is input through the dedicated input signal, MSK_IN.
The shift register circuitry is not necessary for correct operation of PI7C8150B. The shift
register can be eliminated, and MSK_IN can be tied LOW to enable all secondary clock
outputs or tied HIGH to force all secondary clock outputs HIGH. Table 10-2 shows the
format of the serial stream.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| PI7C8150BNDIE-33 | 功能描述:外围驱动器与原件 - PCI 2 Port 32B PCI Bridge RoHS:否 制造商:PLX Technology 工作电源电压: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:FCBGA-1156 封装:Tray |
| PI7C8150DMAE | 功能描述:外围驱动器与原件 - PCI 2-Port PCI Bridge RoHS:否 制造商:PLX Technology 工作电源电压: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:FCBGA-1156 封装:Tray |
| PI7C8150DND | 制造商:Pericom Semiconductor Corporation 功能描述:BRIDGE 制造商:Pericom Semiconductor Corporation 功能描述:2 PORT PCI BRIDGE - Rail/Tube |
| PI7C8150DNDE | 功能描述:外围驱动器与原件 - PCI 2-Port PCI Bridge RoHS:否 制造商:PLX Technology 工作电源电压: 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:FCBGA-1156 封装:Tray |
| PI7C8150EVB | 功能描述:界面开发工具 2 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 产品:Evaluation Boards 类型:RS-485 工具用于评估:ADM3485E 接口类型:RS-485 工作电源电压:3.3 V |
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