参数资料
型号: PI7C8150BNDIE
厂商: Pericom
文件页数: 98/109页
文件大小: 0K
描述: IC PCI-PCI BRIDGE ASYNC 256-PBGA
标准包装: 90
系列: *
应用: *
接口: *
电源电压: *
封装/外壳: 256-BGA
供应商设备封装: 256-PBGA(17x17)
包装: 管件
安装类型: 表面贴装
PI7C8150B
ASYNCHRONOUS 2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 89 of 109
April 2009 – Revision 1.08
Bit
Function
Type
Description
1
Posted Write
Parity Error
R/W
Controls PI7C8150B’s ability to assert P_SERR_L when it is unable
to transfer any read data from the target after 2
24 attempts.
0: P_SERR_L is asserted if this event occurs and the SERR_L enable
bit in the command register is set.
1: P_SERR_L is not assert if this event occurs.
Reset to 0
2
Posted Write
Non-Delivery
R/W
Controls PI7C8150B’s ability to assert P_SERR_L when it is unable
to transfer delayed write data after 2
24 attempts.
0: P_SERR_L is asserted if this event occurs and the SERR_L enable
bit in the command register is set
1: P_SERR_L is not asserted if this event occurs
Reset to 0
3
Target Abort
During Posted
Write
R/W
Controls PI7C8150B’s ability to assert P_SERR_L when it receives a
target abort when attempting to deliver posted write data.
0: P_SERR_L is asserted if this event occurs and the SERR_L enable
bit in the command register is set
1: P_SERR_L is not asserted if this event occurs
Reset to 0
4
Master Abort On
Posted Write
R/W
Controls PI7C8150B’s ability to assert P_SERR_L when it receives a
master abort when attempting to deliver posted write data.
0: P_SERR# is asserted if this event occurs and the SERR# enable bit
in the command register is set
1: P_SERR# is not asserted if this event occurs
Reset to 0
5
Delayed Write
Non-Delivery
R/W
Controls PI7C8150B’s ability to assert P_SERR# when it is unable to
transfer delayed write data after 2
24 attempts.
0: P_SERR_L is asserted if this event occurs and the SERR_L enable
bit in the command register is set
1: P_SERR_L is not asserted if this event occurs
Reset to 0
6
Delayed Read –
No Data From
Target
R/W
Controls PI7C8150B’s ability to assert P_SERR_L when it is unable
to transfer any read data from the target after 2
24 attempts.
0: P_SERR_L is asserted if this event occurs and the SERR_L enable
bit in the command register is set
1: P_SERR_L is not asserted if this event occurs
Reset to 0
7
Reserved
R/O
Reserved. Returns 0 when read. Reset to 0
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