参数资料
型号: PIC12F1822-I/MF
厂商: Microchip Technology
文件页数: 17/109页
文件大小: 0K
描述: IC MCU 8BIT FLASH 8DFN
产品培训模块: 8-bit PIC® Microcontroller Portfolio
标准包装: 120
系列: PIC® XLP™ 12F
核心处理器: PIC
芯体尺寸: 8-位
速度: 32MHz
连通性: I²C,LIN,SPI,UART/USART
外围设备: 欠压检测/复位,POR,PWM,WDT
输入/输出数: 6
程序存储器容量: 3.5KB(2K x 14)
程序存储器类型: 闪存
EEPROM 大小: 256 x 8
RAM 容量: 128 x 8
电压 - 电源 (Vcc/Vdd): 1.8 V ~ 5.5 V
数据转换器: A/D 4x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 8-VDFN 裸露焊盘
包装: 管件
206
7674F–AVR–09/09
ATmega164P/324P/644P
18.8
Register Description
The following section describes the registers used for SPI operation using the USART.
18.8.1
UDRn – USART MSPIM I/O Data Register
The function and bit description of the USART data register (UDRn) in MSPI mode is identical to
18.8.2
UCSRnA – USART MSPIM Control and Status Register n A
Bit 7 - RXCn: USART Receive Complete
This flag bit is set when there are unread data in the receive buffer and cleared when the receive
buffer is empty (i.e., does not contain any unread data). If the Receiver is disabled, the receive
buffer will be flushed and consequently the RXCn bit will become zero. The RXCn Flag can be
used to generate a Receive Complete interrupt (see description of the RXCIEn bit).
Bit 6 - TXCn: USART Transmit Complete
This flag bit is set when the entire frame in the Transmit Shift Register has been shifted out and
there are no new data currently present in the transmit buffer (UDRn). The TXCn Flag bit is auto-
matically cleared when a transmit complete interrupt is executed, or it can be cleared by writing
a one to its bit location. The TXCn Flag can generate a Transmit Complete interrupt (see
description of the TXCIEn bit).
Bit 5 - UDREn: USART Data Register Empty
The UDREn Flag indicates if the transmit buffer (UDRn) is ready to receive new data. If UDREn
is one, the buffer is empty, and therefore ready to be written. The UDREn Flag can generate a
Data Register Empty interrupt (see description of the UDRIE bit). UDREn is set after a reset to
indicate that the Transmitter is ready.
Bit 4:0 - Reserved Bits in MSPI mode
When in MSPI mode, these bits are reserved for future use. For compatibility with future devices,
these bits must be written to zero when UCSRnA is written.
Bit
7
6
5
4
3
2
1
0
RXCn
TXCn
UDREn
-
UCSRnA
Read/Write
R/W
R
Initial Value
0
1
0
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