参数资料
型号: PIC12F1822-I/MF
厂商: Microchip Technology
文件页数: 19/109页
文件大小: 0K
描述: IC MCU 8BIT FLASH 8DFN
产品培训模块: 8-bit PIC® Microcontroller Portfolio
标准包装: 120
系列: PIC® XLP™ 12F
核心处理器: PIC
芯体尺寸: 8-位
速度: 32MHz
连通性: I²C,LIN,SPI,UART/USART
外围设备: 欠压检测/复位,POR,PWM,WDT
输入/输出数: 6
程序存储器容量: 3.5KB(2K x 14)
程序存储器类型: 闪存
EEPROM 大小: 256 x 8
RAM 容量: 128 x 8
电压 - 电源 (Vcc/Vdd): 1.8 V ~ 5.5 V
数据转换器: A/D 4x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 8-VDFN 裸露焊盘
包装: 管件
208
7674F–AVR–09/09
ATmega164P/324P/644P
18.8.4
UCSRnC – USART MSPIM Control and Status Register n C
Bit 7:6 - UMSELn1:0: USART Mode Select
These bits select the mode of operation of the USART as shown in Table 18-4. See “UCSRnC –
USART Control and Status Register n C” on page 192 for full description of the normal USART
operation. The MSPIM is enabled when both UMSELn bits are set to one. The UDORDn,
UCPHAn, and UCPOLn can be set in the same write operation where the MSPIM is enabled.
Bit 5:3 - Reserved Bits in MSPI mode
When in MSPI mode, these bits are reserved for future use. For compatibility with future devices,
these bits must be written to zero when UCSRnC is written.
Bit 2 - UDORDn: Data Order
When set to one the LSB of the data word is transmitted first. When set to zero the MSB of the
data word is transmitted first. Refer to the Frame Formats section page 4 for details.
Bit 1 - UCPHAn: Clock Phase
The UCPHAn bit setting determine if data is sampled on the leasing edge (first) or tailing (last)
edge of XCKn. Refer to the SPI Data Modes and Timing section page 4 for details.
Bit 0 - UCPOLn: Clock Polarity
The UCPOLn bit sets the polarity of the XCKn clock. The combination of the UCPOLn and
UCPHAn bit settings determine the timing of the data transfer. Refer to the SPI Data Modes and
Timing section page 4 for details.
18.8.5
UBRRnL and UBRRnH –USART MSPIM Baud Rate Registers
The function and bit description of the baud rate registers in MSPI mode is identical to normal
Bit
7
6
543
2
1
0
UMSELn1
UMSELn0
-
UDORDn
UCPHAn
UCPOLn
UCSRnC
Read/Write
R/W
R
R/W
Initial Value
0
1
0
Table 18-4.
UMSELn Bits Settings
UMSELn1
UMSELn0
Mode
0
Asynchronous USART
0
1
Synchronous USART
1
0
(Reserved)
1
Master SPI (MSPIM)
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