参数资料
| 型号： | PIC12F1822-I/MF |
| 厂商： | Microchip Technology |
| 文件页数： | 52/109页 |
| 文件大小： | 0K |
| 描述： | IC MCU 8BIT FLASH 8DFN |
| 产品培训模块： | 8-bit PIC® Microcontroller Portfolio |
| 标准包装： | 120 |
| 系列： | PIC® XLP™ 12F |
| 核心处理器： | PIC |
| 芯体尺寸： | 8-位 |
| 速度： | 32MHz |
| 连通性： | I²C，LIN，SPI，UART/USART |
| 外围设备： | 欠压检测/复位，POR，PWM，WDT |
| 输入/输出数： | 6 |
| 程序存储器容量： | 3.5KB（2K x 14） |
| 程序存储器类型： | 闪存 |
| EEPROM 大小： | 256 x 8 |
| RAM 容量： | 128 x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 1.8 V ~ 5.5 V |
| 数据转换器： | A/D 4x10b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 8-VDFN 裸露焊盘 |
| 包装： | 管件 |
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238
7674F–AVR–09/09
ATmega164P/324P/644P
19.9.4
TWDR – TWI Data Register
In Transmit mode, TWDR contains the next byte to be transmitted. In Receive mode, the TWDR
contains the last byte received. It is writable while the TWI is not in the process of shifting a byte.
This occurs when the TWI Interrupt Flag (TWINT) is set by hardware. Note that the Data Regis-
ter cannot be initialized by the user before the first interrupt occurs. The data in TWDR remains
stable as long as TWINT is set. While data is shifted out, data on the bus is simultaneously
shifted in. TWDR always contains the last byte present on the bus, except after a wake up from
a sleep mode by the TWI interrupt. In this case, the contents of TWDR is undefined. In the case
of a lost bus arbitration, no data is lost in the transition from Master to Slave. Handling of the
ACK bit is controlled automatically by the TWI logic, the CPU cannot access the ACK bit directly.
Bits 7:0 – TWD: TWI Data Register
These eight bits constitute the next data byte to be transmitted, or the latest data byte received
on the 2-wire Serial Bus.
19.9.5
TWAR – TWI (Slave) Address Register
The TWAR should be loaded with the 7-bit Slave address (in the seven most significant bits of
TWAR) to which the TWI will respond when programmed as a Slave Transmitter or Receiver,
and not needed in the Master modes. In multimaster systems, TWAR must be set in masters
which can be addressed as Slaves by other Masters.
The LSB of TWAR is used to enable recognition of the general call address (0x00). There is an
associated address comparator that looks for the slave address (or general call address if
enabled) in the received serial address. If a match is found, an interrupt request is generated.
Bits 7:1 – TWA: TWI (Slave) Address Register
These seven bits constitute the slave address of the TWI unit.
Bit 0 – TWGCE: TWI General Call Recognition Enable Bit
If set, this bit enables the recognition of a General Call given over the 2-wire Serial Bus.
19.9.6
TWAMR – TWI (Slave) Address Mask Register
Bits 7:1 – TWAM: TWI Address Mask
Bit
76543210
TWD7
TWD6
TWD5
TWD4
TWD3
TWD2
TWD1
TWD0
TWDR
Read/Write
R/W
Initial Value
11111111
Bit
76543210
TWA6
TWA5
TWA4
TWA3
TWA2
TWA1
TWA0
TWGCE
TWAR
Read/Write
R/W
Initial Value
11111110
Bit
76543210
TWAM[6:0]
–
TWAMR
Read/Write
R/W
R
Initial Value
00000000
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