
PM73487 QRT
PMC-Sierra, Inc.
PMC-980618
Issue 3
622 Mbps ATMTraffic Management Device
Released
Datasheet
164
8.4.2.2
TX_SC_STATE (Internal Structure)
Offset: 1
h
(4
h
byte)
Type: Read/Write – Do not write while SW_RESET (refer to
“SW_RESET” on
page 101
) is deasserted.
Format: Refer to the following table.
8.4.3
Transmit Multicast SC Control Block Summary
Base address: 1200C0
h
(480300
h
byte)
Index: 4
h
Number of entries: 8 (64 words)
Type: Read/Write – Do not write while SW_RESET (refer to
“SW_RESET” on
page 101
) is deasserted.
Long address = 200C0
h
+ 8
h
× (
service_class mod 8)
+
offset
Byte address = 480300
h
+ 20
h
× (
service_class mod 8)
+
offset
Field (Bits)
Description
Not present
(31:16)
RAM is not present in these bit locations.
TX_SC_CONG_ST
(15)
Congestion state bit for the SC congestion determination. Initialize to 0. This bit is read-
only while cells are flowing.
TX_SC_CUR_QD
(14:0)
Current SCQ depth. This is the count of the cells queued in all SC N across the VOs. Ini-
tialize to 0000
h
. This field is maintained by a state machine and is read-only after initial-
ization.
Table 30. Transmit Multicast SC Control Block Summary
Byte
Offset
Long
Offset
Name
Read or
Write
Description
0
h
0
h
TX_SC_MC_IN_FIFO_HEAD
R/W
Head of the multicast input FIFO for this SC.
4
h
1
h
TX_SC_MC_IN_FIFO_TAIL
R/W
Tail of the multicast input FIFO for this SC.
8
h
2
h
TX_SC_MC_BOTTLE
R/W
Bottlenecked VO for multicast in this SC.
C
h
3
h
TX_SC_MC_NEXT_HEADER_PTR
R/W
The next multicast linked list entry (refer to sec-
tion
“MC_LIST” on page 195
) to be transferred
into an SCQ output FIFO.
10-1C
h
4-7
h
Reserved
R/W
Initialize to 0 at initial setup. Software modifi-
cations to this location after setup may cause
incorrect operation.