
PMC-Sierra, Inc.
PM73488 QSE
L
PMC-980616
Issue 3
5 Gbit/s ATMSwitch Fabric Element
Released
Datasheet
29
This arbitration occurs among all cells in the cell buffers and occurs for all 32 ports. In effect, arbitration occurs for
output ports in sequence, starting with cells arbitrating for port 0, then for port 1, and continuing on until port 31
(even though the actual implementation uses a parallel algorithm).
Multicast cells that have won this arbitration then compete with unicast cells for access to the output ports. In this
contention, the cell with the highest priority wins and ties are broken randomly according to the programmable ratio
set in the UC/MC_FAIRNESS_REGISTER (refer to
section 9.3.6 “UC/MC_FAIRNESS_REGISTER” on page 97
).
All these operations are optimized so that, in the absence of congestion, it is possible for a multicast cell to leave the
QSE in the cell time immediately after it arrived.
As mentioned before, the queue completion register (32-bit vector) indicates the outputs to which each multicast cell
needs to go. As a cell goes out on its desired outputs, the appropriate bits in the queue completion register are cleared.
When all bits in the queue completion register have been cleared, the cell is deleted from the internal buffers and the
buffer is reused for new incoming traffic.