参数资料
型号: PM73488-PI
厂商: PMC-SIERRA INC
元件分类: 数字传输电路
英文描述: 5 Gbit/s ATM Switch Fabric Element
中文描述: ATM SWITCHING CIRCUIT, PBGA596
封装: EPBGA-596
文件页数: 40/135页
文件大小: 1735K
代理商: PM73488-PI
PMC-Sierra, Inc.
PM73488 QSE
L
PMC-980616
Issue 3
5 Gbit/s ATMSwitch Fabric Element
Released
Datasheet
42
3.1.3
BP_ACK Encodings
The BP_ACK encodings (BP_ACK_IN and BP_ACK_OUT) guarantee transitions, and BP and ACK encodings are
shown in Figure 29.
The BP_ACK signal is used to signal backpressure/cell acknowledgment to the previous stage. To ensure the transi-
tions required by the phase aligner, this line carries a repeating four “0s” and four “1s” pattern. The actual informa-
tion is transferred by a break in this pattern (shown by BP_ACK signaling in Figure 29). The pattern break is
identified by a bit inversion (Inversion 1) on the line, followed by a mode, and two data bits, followed by a second
inversion (Inversion2) of the expected bit, if the previous pattern had continued. This is followed by the last two bits.
After these information bits, the repeating pattern restarts with four “0s”.
3
IDLE_2
IDLE_2 = 0100
b
: Marching 1 pattern, which protects
against bridging faults.
4
IDLE_3
IDLE_3 = 0010
b
: Marching 1 pattern, which protects
against bridging faults.
5
IDLE_4
IDLE_4 = 0001
b
: Marching 1 pattern, which protects
against bridging faults.
6
IDLE_5
IDLE_5 = 0000
b
:
7
IDLE_6
IDLE_6 = 0000
b
.
8-15
Reserved
(QSE currently outputs 0000
b
.)
16-117
Unused
(QSE currently outputs 0000
b
.)
Figure 29. BP_ACK Encodings
Table 6. PM73488 Mode Idle Cell Format (Continued)
Nibble
Symbol
Definition
Comment
Four 1s
Four 0s
Four 1s
Four 0s
Four 0s
Four 1s
Inversion 1
Mode
Data3
Data2
Inversion 2
Data1
Data0
SE_CLK
BP_ACK Base Pattern
BP_ACK Signaling
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