
PMC-Sierra, Inc.
PM73488 QSE
L
PMC-980616
Issue 3
5 Gbit/s ATMSwitch Fabric Element
Released
Datasheet
72
6.4.1
Processor Interface Signals
Table 16. Processor Interface Signals (21 Signal Pins)
Signal Name
Ball
#
# of
Pins
Type
Description
ADD(7:0)
AJ7, AH9, AG10,
AF10, AK4, AH8,
AG9, AK3
8
In
Address Bits 7to 0
are part of the 8-bit processor address
bus.
DATA(7:0)
AJ9, AH10,
AG11, AE13,
AE12, AJ8, AF11,
AK6
8
Bi 3
Data Bits 7 to 0 are
part of the 8-bit processor data bus.
/CS
AK7
1
In
Chip Select
is an active low signal that selects the device
for processor access.
/RD
AK8
1
In
Read
is an active low signal that selects a read cycle.
/WR
AH12
1
In
Write
is an active low signal that selects a write cycle.
/ACK
AJ11
1
Out 5
Acknowledge
is an active low signal that indicates the
processor cycle is finished.
/INTR
AG13
1
Out 5
Interrupt
indicates an interrupt is present.
6.4.2
Multicast RAM Interface Signals
Table 17. Multicast RAM Interface Signals (39 Signal Pins)
Signal Name
Ball
#
# of
Pins
Type
Description
RAM_ADD(18:0)
AF12, AH1, F18,
C27, E23, E24,
D24, F24, D26,
D25, E25, A29,
B30, F26, F27,
E27, G25, G27,
G26
19
Out 5
RAM Address Bits 18 to 0
are part of the 19-bit SRAM
address bus.
RAM_DATA(15:0)
C22, E20, A27,
B24, D22, D21,
E21, E22, C23,
B27, A28, C25,
B26, F21, B28,
F22
16
Bi 3
RAM Data Bits 15 to 0 are
part of the 16-bit SRAM data
bus.
RAM_PARITY
F19
1
Bi 3
Parity for the RAM Data bits. Generated and checked by
the QSE.
B23
1
Out 8
RAM Clock.