
PMC-Sierra, Inc.
PM73488 QSE
L
PMC-980616
Issue 3
5 Gbit/s ATMSwitch Fabric Element
Released
Datasheet
87
8.2
The RAM interface is a synchronous interface, with respect to the RAM_CLK. Each read or write operation lasts for
at least two clock cycles because of the internal 32-bit data bus. Recall that the RAM_DATA bus is covered by one
bit of parity, named RAM_PARITY; this parity bit signal follows the same timing constraints and timing guarantees
as the rest of the data bus.
RAM Timing
Tqd
Tvdk
SE_CLK-to-output delay
Data valid prior to /ACK
assertion
Data valid after /CS or /WR,
whichever is low last
Address valid after /CS, /RD, or
/WR, whichever is low last
Address hold after /ACK
assertion
Data hold after /ACK assertion
for write cycle
Hold time after /CS, /RD, or /
WR, whichever is high first
Wait time between two
consecutive cycles
DATA(7:0)
DATA(7:0)
1
SE_CLK
cycle - 10.3
13.5
ns
ns
Tvd
DATA(7:0)
1
SE_CLK
cycle
SE_CLK
cycles
ns
Tva
ADD(7:0)
1
Tha
ADD(7:0)
0
Thd
DATA(7:0)
0
ns
Thc
/ACK, DATA(7:0)
1.2
ns
Twcy
/CS, /RD, /WR
1
SE_CLK
cycles
Figure 38. RAM Interface
Table 28.
RAM Interface Timing
Symbol
Parameter
Conditions
Min
Max
Unit
SE_CLK to RAM_CLK
RAM_CLK
0.5
2.5
ns
Table 27.
Microprocessor Timing (Continued)
Symbol
Parameter
Conditions
Min
Max
Unit
Tck
Tsd
Thd
Tq
Tq
Tqa
Tqa
Tq
SE_CLK
RAM_CLK
/RAM_WR
/RAM_OE
RAM_ADD
RAM_DATA