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| 型号： | PowerPC 740 |
| 厂商： | IBM Microeletronics |
| 英文描述： | 32-Bit Embedded Microprocessor(32位精简指令集嵌入式微处理器) |
| 中文描述： | 32位嵌入式微处理器（32位精简指令集嵌入式微处理器） |
| 文件页数： | 13/48页 |
| 文件大小： | 608K |
| 代理商： | POWERPC 740 |
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12/8/99
Version 1.02
Page13
PowerPC 740 and PowerPC 750 Microprocessor
CMOS 0.20
μ
m Copper Technology, PID-8p, PPC740L and PPC750L, dd3.2
AC Electrical Characteristics
This section provides the AC electrical characteristics for the 750. After fabrication, parts are sorted by maxi-
mum processor core frequency as shown in the Section “Clock AC Specifications,” on page 13, and tested for
conformance to the AC specifications for that frequency. Parts are sold by maximum processor core fre-
quency, subject to the specified application conditions; see Section “Ordering Information,” on page 46.
Unless otherwise noted, all timings apply for all I/O supply voltages.
Clock AC Specifications
The following table provides the clock AC timing specifications as defined in Figure 2.
Clock AC Timing Specifications
See Table “Recommended Operating Conditions,” on page 9, for operating conditions.
Num
Characteristic
Fmax = 300-375MHz
Fmax
≥
400MHz
Unit
Notes
Min
Max
Min
Max
Processor frequency
TBD
As specified by
part number
250
As specified by
part number
MHz
6
SYSCLK frequency
25
100
31
100
MHz
1
1
SYSCLK cycle time
10
40
10
32
ns
2,3
SYSCLK rise and fall time
–
1.0
–
1.0
ns
2,3
4
SYSCLKdutycyclemeasured
at Vm
40
60
40
60
%
3
SYSCLK jitter
–
±
150
–
±
150
ps
4,3
Internal PLL relock time
–
100
–
100
μ
s
5
Note:
1. Caution: The SYSCLK frequency and the PLL_CFG[0:3] settings must be chosen such that the resulting SYSCLK (bus) frequency, and CPU (core)
frequency do not exceed their respective maximum or minimum operating frequencies. Refer to the PLL_CFG[0:3] signal description in Section “PLL
Configuration,” on page 36 for valid PLL_CFG[0:3] settings. Bus operation above 100 MHz is possible, but requires careful timing analysis. Contact
IBM for details.
2. Rise and fall times for the SYSCLK input are measured from 0.5 to 1.5V.
3. Timing is guaranteed by design and characterization, and is not tested.
4. The total input jitter (short term and long term combined) must be under
±
150ps. Contact IBM for operation with Spread Spectrum clocks or clocks
with more than
±
150 ps total jitter.
5. Relock timing is guaranteed by design and characterization, and is not tested. PLL-relock time is the maximum amount of time required for PLL lock
after a stable V
and SYSCLK are reached during the power-on reset sequence. This specification also applies when the PLL has been disabled and
subsequently re-enabled during sleep mode. Also note that HRESET must be held asserted for a minimum of 255 bus clocks after the PLL-relock time
during the power-on reset sequence.
6. Under certain conditions, operation at core frequencies below those stated is possible. Contact IBM for details.
Figure 2. SYSCLK Input Timing Diagram
VM
CV
IL
CV
IH
1
2
4
3
4
SYSCLK
Vm = OVdd/2
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