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| 型号： | PowerPC 740 |
| 厂商： | IBM Microeletronics |
| 英文描述： | 32-Bit Embedded Microprocessor(32位精简指令集嵌入式微处理器) |
| 中文描述： | 32位嵌入式微处理器（32位精简指令集嵌入式微处理器） |
| 文件页数： | 14/48页 |
| 文件大小： | 608K |
| 代理商： | POWERPC 740 |
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Page 14
Version 1.02
12/8/99
PowerPC 740 and PowerPC 750 Microprocessor
CMOS 0.20
μ
m Copper Technology, PID-8p, PPC740L and PPC750L, dd3.2
60x Bus Input AC Specifications
The following table provides the 60X bus input AC timing specifications for the 750 as defined in Figure 3 and
Figure 4. Input timing specifications for the L2 bus are provided in Section, “L2 Bus Input AC Specifications”
on page 20.
60X Bus Input Timing Specifications
1
See Table “Recommended Operating Conditions,” on page 9, for operating conditions.
Num
Characteristic
All Frequencies
Unit
Notes
Minimum
Maximum
10a
Address/Data/Transfer Attribute Inputs Valid to SYSCLK (Input
Setup)
2.5
—
ns
2
10b
All Other Inputs Valid to SYSCLK (Input Setup)
2.5
—
ns
3
10c
Mode Select Input Setup to HRESET (DRTRY,TLBISYNC)
8
—
t
sysclk
4,5,6,7
11a
SYSCLK to Address/Data/Transfer Attribute Inputs Invalid (Input
Hold)
0.6
—
ns
2
11b
SYSCLK to All Other Inputs Invalid (Input Hold)
0.6
—
ns
3
11c
HRESET to mode select input hold (DRTRY, TLBISYNC)
0
—
ns
4,6,7
Note:
1. Input specifications are measured from the Vm of the signal in question to the Vm of the rising edge of the input SYSCLK. Input and output timings are
measured at the pin (see Figure 3
2. Address/Data Transfer Attribute inputs are composed of the following–A[0:31], AP[0:3], TT[0:4],TBST, TSIZ[0:2], GBL, DH[0:31], DL[0:31], DP[0:7].
3. All other signal inputs are composed of the following–TS, ABB, DBB, ARTRY, BG, AACK, DBG, DBWO, TA, DRTRY, TEA, DBDIS, TBEN, QACK,
TLBISYNC.
4. The setup and hold time is with respect to the rising edge of HRESET (see Figure 4).
5. t
, is the period of the external clock (SYSCLK) in nanoseconds (ns). The numbers given in the table must be multiplied by the period of SYSCLK
to compute the actual time duration (in ns) of the parameter in question.
6. These values are guaranteed by design, and are not tested.
7. This specification is for configuration mode select only. Also note that the HRESET must be held asserted for a
minimum of 255 bus clocks
after the
PLL re-lock time during the power-on reset sequence.
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