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| 型号： | PowerPC 740 |
| 厂商： | IBM Microeletronics |
| 英文描述： | 32-Bit Embedded Microprocessor(32位精简指令集嵌入式微处理器) |
| 中文描述： | 32位嵌入式微处理器（32位精简指令集嵌入式微处理器） |
| 文件页数： | 38/48页 |
| 文件大小： | 608K |
| 代理商： | POWERPC 740 |
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Page 38
Version 1.02
12/8/99
PowerPC 740 and PowerPC 750 Microprocessor
CMOS 0.20
μ
m Copper Technology, PID-8p, PPC740L and PPC750L, dd3.2
External clock routing should ensure that the rising edge of the L2 clock is coincident at the CLK input of all
SRAMs and at the L2SYNC_IN input of the 750. The L2CLKOUTA network could be used only, or the
L2CLKOUTB network could also be used depending on the loading, frequency, and number of SRAMs.
Output Buffer DC Impedance
The 750 60x and L2 I/O drivers were characterized over process, voltage, and temperature. To measure Z
0
,
an external resistor is connected to the chip pad, either to OV
DD
or GND. Then the value of such resistor is
varied until the pad voltage is OV
DD
/2; see Figure 19, “Driver Impedance Measurement,” below.
The output impedance is actually the average of two components, the resistances of the pull-up and pull-
down devices. When Data is held low, SW1 is closed (SW2 is open), and R
N
is trimmed until Pad = OV
DD
/2. R
N
then becomes the resistance of the pull-down devices. When Data is held high, SW2 is closed (SW1 is open),
and R
P
is trimmed until Pad = OV
DD
/2. R
P
then becomes the resistance of the pull-up devices. With a properly
designed driver R
P
and R
N
are close to each other in value, then Z
0
= (R
P
+ R
N
)/2.
The following table summarizes the impedance a board designer would design to for a typical process. These
values were derived by simulation at 65
°
C. As the process improves, the output impedance will be lower by
several ohms than this typical value.
Figure 19. Driver Impedance Measurement
Impedance Characteristics
V
DD
= 1.9V
DC
, L2OV
DD
=OV
DD
= 3.3V
DC
, T
J
=
65
°
C
Process
60x
L2
Symbol
Unit
Typical
43
38
Z
0
Data
OV
DD
R
N
SW2
SW1
Pad
R
P
GND
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