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参数资料
| 型号： | Q80C32-30SHXXX:RD |
| 厂商： | TEMIC SEMICONDUCTORS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, 30 MHz, MICROCONTROLLER, CQFP44 |
| 文件页数： | 20/83页 |
| 文件大小： | 8336K |
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195
7679H–CAN–08/08
AT90CAN32/64/128
17.11 USART Register Description
17.11.1
USART0 I/O Data Register – UDR0
17.11.2
USART1 I/O Data Register – UDR1
Bit 7:0 – RxBn7:0: Receive Data Buffer (read access)
Bit 7:0 – TxBn7:0: Transmit Data Buffer (write access)
The USARTn Transmit Data Buffer Register and USARTn Receive Data Buffer Registers share
the same I/O address referred to as USARTn Data Register or UDRn. The Transmit Data Buffer
Register (TXBn) will be the destination for data written to the UDRn Register location. Reading
the UDRn Register location will return the contents of the Receive Data Buffer Register (RXBn).
For 5-, 6-, or 7-bit characters the upper unused bits will be ignored by the Transmitter and set to
zero by the Receiver.
The transmit buffer can only be written when the UDREn flag in the UCSRnA Register is set.
Data written to UDRn when the UDREn flag is not set, will be ignored by the USARTn Transmit-
ter. When data is written to the transmit buffer, and the Transmitter is enabled, the Transmitter
will load the data into the Transmit Shift Register when the Shift Register is empty. Then the
data will be serially transmitted on the TxDn pin.
The receive buffer consists of a two level FIFO. The FIFO will change its state whenever the
receive buffer is accessed.
17.11.3
USART0 Control and Status Register A – UCSR0A
17.11.4
USART1 Control and Status Register A – UCSR1A
Bit 7 – RXCn: USARTn Receive Complete
This flag bit is set when there are unread data in the receive buffer and cleared when the receive
buffer is empty (i.e., does not contain any unread data). If the Receiver is disabled, the receive
buffer will be flushed and consequently the RXCn bit will become zero. The RXCn flag can be
used to generate a Receive Complete interrupt (see description of the RXCIEn bit).
Bit
7
6
543
210
RXB0[7:0]
UDR0 (Read)
TXB0[7:0]
UDR0 (Write)
Read/Write
R/W
Initial Value
0
Bit
7
6
543
210
RXB1[7:0]
UDR1 (Read)
TXB1[7:0]
UDR1 (Write)
Read/Write
R/W
Initial Value
0
Bit
765
4321
0
RXC0
TXC0
UDRE0
FE0
DOR0
UPE0
U2X0
MPCM0
UCSR0A
Read/Write
R
R/W
R
R/W
Initial Value
001
0000
0
Bit
765
4321
0
RXC1
TXC1
UDRE1
FE1
DOR1
UPE1
U2X1
MPCM1
UCSR1A
Read/Write
R
R/W
R
R/W
Initial Value
001
0000
0
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