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参数资料
| 型号： | Q80C32-30SHXXX:RD |
| 厂商： | TEMIC SEMICONDUCTORS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, 30 MHz, MICROCONTROLLER, CQFP44 |
| 文件页数： | 74/83页 |
| 文件大小： | 8336K |
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86
7707F–AVR–11/10
AT90USB82/162
12.0.3
External Interrupt Mask Register – EIMSK
Bits 7..0 – INT7 – INT0: External Interrupt Request 7 - 0 Enable
When an INT7 – INT0 bit is written to one and the I-bit in the Status Register (SREG) is set
(one), the corresponding external pin interrupt is enabled. The Interrupt Sense Control bits in the
External Interrupt Control Registers – EICRA and EICRB – defines whether the external inter-
rupt is activated on rising or falling edge or level sensed. Activity on any of these pins will trigger
an interrupt request even if the pin is enabled as an output. This provides a way of generating a
software interrupt.
12.0.4
External Interrupt Flag Register – EIFR
Bits 7..0 – INTF7 - INTF0: External Interrupt Flags 7 - 0
When an edge or logic change on the INT7:0 pin triggers an interrupt request, INTF7:0 becomes
set (one). If the I-bit in SREG and the corresponding interrupt enable bit, INT7:0 in EIMSK, are
set (one), the MCU will jump to the interrupt vector. The flag is cleared when the interrupt routine
is executed. Alternatively, the flag can be cleared by writing a logical one to it. These flags are
always cleared when INT7:0 are configured as level interrupt. Note that when entering sleep
mode with the INT3:0 interrupts disabled, the input buffers on these pins will be disabled. This
may cause a logic change in internal signals which will set the INTF3:0 flags. See “Digital Input
Enable and Sleep Modes” on page 71 for more information.
12.0.5
Pin Change Interrupt Control Register - PCICR
Bit 1..0 – PCIE1- PCIE0: Pin Change Interrupt Enable 1-0
When the PCIE1/0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),
Pin Change interrupt 1/0 is enabled. Any change on any enabled PCINT12..8/7..0 pin will
cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is exe-
cuted from the PCI1/0 Interrupt Vector. PCINT12..8/7..0 pins are enabled individually by the
PCMSK1/0 Register.
12.0.6
Pin Change Interrupt Flag Register – PCIFR
Bit 1..0 – PCIF1- PCIF0: Pin Change Interrupt Flag 1-0
Bit
7654
3
2
1
0
INT7
INT6
INT5
INT4
INT3
INT2
INT1
IINT0
EIMSK
Read/Write
R/WR/W
Initial Value
0000
0
Bit
7654
3
2
1
0
INTF7
INTF6
INTF5
INTF4
INTF3
INTF2
INTF1
INTF0
EIFR
Read/Write
R/WR/W
Initial Value
0000
0
Bit
7654
3210
-
–
PCIE1
PCIE0
PCICR
Read/Write
RRRR
RRR/W
R/W
Initial Value
0000
Bit
7654
3210
-
–
PCIF1
PCIF0
PCIFR
Read/Write
RRRR
RRR/W
R/W
Initial Value
0000
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