
PRODUCT SPECIFICATION
RC7102
3
Advanced
Infor
mation
Pin Assignments
Pin Name
Pin Number
Type
Pin Function Description
CPU0:1
43, 44
OUT
CPU Outputs: The CPU clock outputs are controlled by the
CLK_STOP# control pin.
PCI1:5
8, 10, 11, 12, 13
OUT
PCI Clock Outputs 1 through 5: These five PCI clock outputs
are controlled by the PCI_STOP# control pin.
MODE/PCI_F
7
IN/OUT
Fixed PCI Clock Output: Frequency is set by the FS0:2 inputs
or through serial input interface. (see Tables 2 and 6) This
output is not affected by the PCI_STOP# input. Upon power-up
MODE input will be latched, which will enable or disable
SDRAM10 and SDRAM11. (see Tables 1 and 2)
CPU_STOP#/
SDRAM11
17
IN/OUT
CPU_STOP Input: When brought low, the CPU clock outputs
are stopped low after completing a full clock cycle.
IOAPIC
47
OUT
IOAPIC Clock Output: Provides 14.318MHz fixed frequency.
The output voltage swing is controlled by VDDQ2..
48MHz/FS0
26
IN/OUT
48MHz Output: 48MHz is provided in normal operation. In
standard systems, this output can be used as the reference for
the Universal Serial Bus. Upon power-up FS0 input will be
latched, which will set clock frequencies as described in
Table 2.
24MHz/FS1
25
IN/OUT
24MHz Output: 24MHz is provided in normal operation. In
standard systems, this output can be used as the clock input for
a Super I/O chip. Upon power-up FS1 input will be latched,
which will set clock frequencies as described in Table 2.
REF1/FS2
46
IN/OUT
I/O Dual Function REF1 and FS2 pin: Upon power-up, FS2
input will be latched which will set clock frequencies as
described in Table 2. When an output, this pin provides a fixed
clock signal equal in frequency to the reference signal provided
at the X1/X2 pins.
REF0
2
OUT
REF0 output, this pin provides a fixed clock signal equal in
frequency to the reference signal provided at the X1/X2 pins.
SDRAMIN
15
IN
Buffered Input Pin: The signal provided to this input pin is
buffered to 14 outputs (SDRAM0:13).
SDRAM0:13
38, 37, 35, 34,
32, 31, 29, 28,
21, 20, 18, 17,
40, 41
OUT
Buffered Outputs: These fourteen dedicated outputs provide
copies of the signal provided at the SDRAMIN input. The swing
is set by VDDQ3, and if the CPU clock is used to drive the
SDRAMIN then they are deactivated when CPU_STOP# input
is set low.
SCLK
24
IN
Clock pin for I2C Circuitry.
SDATA
23
IN/OUT
Data pin for I2C Circuitry.
X1
4
IN
Crystal Connection or External Reference Frequency
Input: This pin has dual functions. It can be used as an external
14.318MHz crystal connection or as an external reference
frequency input.
PCI_STOP#/
SDRAM10
18
IN/OUT
SDRAM10 or PCI_STOP# Pin: Function determined by MODE
pin. The PCI_STOP# input enables the PCI 1:5 outputs when
high and causes them to remain at logic 0 when low.
X2
5
IN
Crystal Connection: An input connection for an external
14.318MHz crystal. If using an external reference, this pin must
be left unconnected.
VDDQ3
1, 6, 14, 19, 27,
30, 36
POWER
Power Connection: Power supply for core logic, PLL circuitry,
SDRAM outputs, PCI outputs, reference outputs, 48MHz
output, and 24MHz output. Connect to 3.3V supply