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参数资料
| 型号： | RC7102 |
| 厂商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 133.3 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封装： | SSOP-48 |
| 文件页数： | 13/16页 |
| 文件大小： | 72K |
| 代理商： | RC7102 |
RC7102
PRODUCT SPECIFICATION
6
Advanced
Infor
mation
AC Electrical Characteristics
TA = 0°C to +70°C; VDDQ3 = 3.3V±5%; VDDQ2 = 2.5V±5%; f XTL = 14.31818MHz
AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the
clock output; Spread Spectrum clocking is disabled.
CPU Clock Outputs, CPU0:1 (Lump Capacitance Test Load = 20pF)
CPU = 66.6MHz
CPU = 100MHz
Units
Parameter
Min.
Typ. Max. Min.
Typ. Max.
Test Condition/Comments
tP
Period
15
15.5
10
10.5
ns
Measured on rising edge at 1.25.
tH
High Time
5.2
3.0
ns
Duration of clock cycle above 2.0V.
tL
Low Time
5.0
2.8
ns
Duration of clock cycle below 0.4V.
tR
Output Rise Edge Rate
1
4
1
4
V/ns
Measured from 0.4V to 2.0V.
tF
Output Fall Edge Rate
1
4
1
4
V/ns
Measured from 2.0V to 0.4V.
tD
Duty Cycle
45
55
45
55
%
Measured on rising and falling
edge at 1.25V.
tJC
Jitter, Cycle-to-Cycle
250
ps
Measured on rising edge at 1.25V.
Maximum difference of cycle time
between two adjacent cycles.
tSK
Output Skew
175
ps
Measured on rising edge at 1.25V.
fST
Frequency Stabilization
from Power-up
(cold start)
3
ms
Assumes full supply voltage
reached within 1ms from power-
up.
Z0
AC Output Impedance
20
ohm
Average value during switching
transition. Used for determining
series termination value.
PCI Clock Outputs, PCI_F and PCI_1:5 (Lump Capacitance Test Load = 30pF)
CPU = 66.6/
100MHz
Units
Parameter
Min.
Typ. Max.
Test Condition/Comments
tP
Period
30
ns
Measured on rising edge at 1.5V.
tH
High Time
12.0
ns
Duration of clock cycle above 2.4V.
tL
Low Time
12.0
ns
Duration of clock cycle below 0.4V.
tR
Output Rise Edge Rate
1
4
V/ns
Measured from 0.4V to 2.4V.
tF
Output Fall Edge Rate
1
4
V/ns
Measured from 2.4V to 0.4V.
tD
Duty Cycle
45
55
%
Measured on rising and falling edge at 1.5V.
tJC
Jitter, Cycle-to-Cycle
500
ps
Measured on rising edge at 1.5V. Maximum
difference of cycle time between two adjacent
cycles.
tSK
Output Skew
500
ps
Measured on rising edge at 1.5V.
tO
CPU to PCI Clock Skew
1.5
4.0
ns
Covers all CPU/PCI outputs. Measured on rising
edge at 1.5V. CPU leads PCI output.
fST
Frequency Stabilization
from Power-up
(cold start)
ms
Assumes full supply voltage reached within 1ms
from power-up.
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