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参数资料
| 型号： | RC7102 |
| 厂商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 133.3 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封装： | SSOP-48 |
| 文件页数： | 16/16页 |
| 文件大小： | 72K |
| 代理商： | RC7102 |
PRODUCT SPECIFICATION
RC7102
9
Advanced
Infor
mation
Functional Description
I/O Pin Operation
Pins 7, 17, 18, 25, 26, 46 are dual purpose l/O pins. Upon
power up these pins act as logic inputs, allowing the determi-
nation of assigned device functions. A short time after power
up, the logic state of each pin is latched and the pins become
clock outputs. This feature reduces device pin count by com-
bining clock outputs with input select pins.
An external 10k ohm “strapping” resistor is connected
between the l/O pin and ground or VDD. Connection to
ground sets a latch to "0", connection to VDD sets a latch to
"1". Figure 1 and Figure 2 show two suggested methods for
strapping resistor connections.
Upon RC7102 power up, the rst 2ms of operation is used
for input logic selection. During this period, the six I/O
pins(7, 17, 18, 25, 26, 46) are tristated, allowing the output
strapping resistor on the l/O pins to pull the pin and their
associated capacitive clock load to either a logic high or low
state. At the end of the 2ms period, the established logic "0"
or "1" condition of the l/O pin is latched. Next the output
buffer is enabled which converts the l/O pins into operating
clock outputs. The 2ms timer is started when VDD reaches
2.0V. The input bits can only be reset by turning VDD off
and then back on again.
It should be noted that the strapping resistors have no signi-
cant effect on clock output signal integrity. The drive imped-
ance of clock output is <40 ohms (nominal) which is
minimally affected by the 10k ohm strap to ground or VDD.
As with the series termination resistor, the output strapping
resistor should be placed as close to the l/O pin as possible in
order to keep the interconnecting trace short. The trace from
the resistor to ground or VDD should be kept less than two
inches in length to prevent system noise coupling during
input logic sampling.
When the clock outputs are enabled following the 2ms input
period, the specied output frequency is delivered on the pin,
assuming that VDD has stabilized. If VDD has not yet
reached full value, output frequency initially may be below
target but will increase to target once VDD voltage has stabi-
lized. In either case, a short output clock cycle may be pro-
duced from the CPU clock outputs when the outputs are
enabled.
Figure 1. Input Logic Selection through Resistor Load Option
Figure 2. Input Logic Selection through Jumper Option
RC7102
OUTPUT
BUFFER
10k
(LOAD
OPTION 0)
CLOCK
LOAD
10k
(LOAD
OPTION 1)
VDD
OUTPUT
STRAPPING
RESISTOR
SERIES
TERMINATION
RESISTOR
RC7102
OUTPUT
BUFFER
CLOCK
LOAD
10k
JUMPER
OPTIONS
OUTPUT
STRAPPING
RESISTOR
SERIES
TERMINATION
RESISTOR
VALUE R
R
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