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参数资料
| 型号： | RC7102 |
| 厂商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 133.3 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封装： | SSOP-48 |
| 文件页数： | 5/16页 |
| 文件大小： | 72K |
| 代理商： | RC7102 |
PRODUCT SPECIFICATION
RC7102
13
Advanced
Infor
mation
Data Byte 3
7
—
(Reserved)
—
1
6
—
(Reserved)
—
1
5
26
48Mhz
Clock Output Disable
Low
Active
1
4
25
24MHz
Clock Output Disable
Low
Active
1
3
—
(Reserved)
—
1
2
21, 20, 18, 17 SDRAM8:11 Clock Output Disable (SDRAM
10, 11 only when MODE=1)
Low
Active
1
32, 31, 29, 28 SDRAM4:7
Clock Output Disable
Low
Active
1
0
38, 37, 35, 34 SDRAM0:3
Clock Output Disable
Low
Active
1
Data Byte 4
7
—
(Reserved)
—
1
6
—
(Reserved)
—
1
5
—
(Reserved)
—
1
4
—
(Reserved)
—
1
3
—
(Reserved)
—
1
2
—
(Reserved)
—
1
—
(Reserved)
—
1
0
—
(Reserved)
—
1
Data Byte 5
7
—
(Reserved)
—
1
6
—
(Reserved)
—
1
5
—
(Reserved)
—
1
4
47
IOAPIC
Clock Output Disable
Low
Active
1
3
—
(Reserved)
—
1
2
—
(Reserved)
—
1
46
REF1
Clock Output Disable
Low
Active
1
0
2
REF0
Clock Output Disable
Low
Active
1
Table 5. Data Bytes 0-5 Serial Conguration Map (continued)
Bit(s)
Affected Pin
Control Function
Bit Control
Pin No.
Pin Name
0
1
Default
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