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参数资料
| 型号： | RC7102 |
| 厂商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 133.3 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封装： | SSOP-48 |
| 文件页数： | 2/16页 |
| 文件大小： | 72K |
| 代理商： | RC7102 |
RC7102
PRODUCT SPECIFICATION
10
Advanced
Infor
mation
Serial Data Interface
The RC7102 features a two-pin, serial data interface that can
be used to congure internal register settings that control
particular device functions. Upon power-up, the RC7102 ini-
tializes with default register settings, therefore the use of this
serial data interface is optional. The serial interface is write-
only (to the clock chip) and is the dedicated function of
device pins SDATA and SCLOCK. In motherboard applica-
tions, SDATA and SCLOCK are typically driven by two
logic outputs of the chipset. Clock device register changes
are normally made upon system initialization, if any are
required. The interface can also be used during system
operation for power management functions. Table 3 summa-
rizes the control functions of the serial data interface.
Table 3. Serial Data Interface Control Functions Summary
Control Function
Description
Common Applications
Clock Output Disable
Any individual clock output(s) can be
disabled. Disabled outputs are actively
held low.
Unused outputs are disabled to reduce
EMI and system power. Examples are
clock outputs to unused PCI slots.
CPU Clock Frequency
Selection
Provides CPU/PCI frequency selections
through software. Frequency is changed
in a smooth and controlled fashion.
For alternate microprocessors and power
management options. Smooth frequency
transition allows CPU frequency change
under normal system operation.
Spread Spectrum
Enabling
Enables or disables spread spectrum
clocking.
For EMI reduction.
Output Tristate
Puts clock output into a high impedance
state.
Production PCB testing.
(Reserved)
Reserved function for future device
revision or production device testing.
No user application. Register bit must be
written as 0.
Test Mode
All clock outputs toggle in relation to X1
input, internal PLL is bypassed. Refer to
Table 7.
Production PCB Testing
Signaling Requirements for the I2C Serial Port
To initiate communications with the serial port, a start bit is
invoked. The start bit is dened as the SDATA line is brought
low while the SCLOCK is held high. Once the start bit is ini-
tiated, valid data can then be sent. Data is considered to be valid
when the clock goes to and remains in the high state. The
data can change when the clock goes low. To terminate the
transmission, a stop bit is invoked. The stop bit occurs when
the SDATA line goes from a low to a high state while the
SCLOCK is held high. See Figure below.
RC7104 I2C Interface Write Sequence Example
MSB
1
2
3
4
5
6
7
8
A
1
2
3
8
A
1
2
8
A
8
A
1
0
1
0
1
0
MSB
LSB
STOP
START
SDATA
SCLK
SDATA
(ACK Signal
From Buffer Chip)
LSB
Slave Address (First Byte)
Signal from Motherboard Clock Chip
Command Code (2nd Byte)
Byte Count (3rd Byte)
Last Data Byte
Note:
Once the clock detects the start condition and its ADDRESS is matched, the clock chip will pull down the SDATA at every 8th bit. The 8 bit data
from SDATA is latched into the Buffer Chip when the ACK is generated. This ACK signal will continue as long as STOP condition is detected
The COMMAND CODE and BYTE COUNT is not used by the Buffer Chip.
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