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参数资料
| 型号： | RC7102 |
| 厂商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 133.3 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封装： | SSOP-48 |
| 文件页数： | 15/16页 |
| 文件大小： | 72K |
| 代理商： | RC7102 |
RC7102
PRODUCT SPECIFICATION
8
Advanced
Infor
mation
fST
Frequency Stabilization
from Power-up
(cold start)
3
ms
Assumes full supply voltage reached within 1ms
from power-up.
Z0
AC Output Impedance
40
ohm
Average value during switching transition. Used for
determining series termination value.
24MHz Clock Output (Lump Capacitance Test Load = 20pF)
CPU = 66.6MHz
Units
Parameter
Min.
Typ. Max.
Test Condition/Comments
f
Frequency, Actual
24.004
MHz
Determined by PLL divider ratio (see n/m below).
fD
Deviation from 24MHz
+167
ppm
(24.004 – 24)/24
m/n
PLL Ratio
57/34
(14.31818MHz x 57/34 = 24.004MHz)
tR
Output Rise Edge Rate
0.5
2
V/ns
Measured from 0.4V to 2.4V.
tF
Output Fall Edge Rate
0.5
2
V/ns
Measured from 2.4V to 0.4V.
tD
Duty Cycle
45%
55
%
Measured on rising and falling edge at 1.5V.
fST
Frequency Stabilization
from Power-up
(cold start)
3
ms
Assumes full supply voltage reached within 1ms
from power-up.
Z0
AC Output Impedance
40
ohm
Average value during switching transition. Used for
determining series termination value.
SDRAM Clock Outputs, SDRAM0:13 (Lump Capacitance Test Load =30pF)
Parameter
Min.
Typ.
Max.
Units
Test Conditions/Comments
fIN
Input Frequency
0
150
MHz
tR
Output Rise Time
0.5
1.33
nS
Measured from 0.4V to 2.4V
tF
Output Fall Time
0.5
1.33
nS
Measured from 2.4V to 0.4V
tSR
Output Skew, Rising Edge
250
pS
tSF
Output Skew, Falling Edge
250
pS
tEN
Output Enable Time
1.0
8.0
nS
tDIS
Output Disable Time
1.0
8.0
nS
tPR
Rising Edge Propagation Delay
1.0
5.0
nS
tPF
Falling Edge Propagation Delay
1.0
5.0
nS
tD
Duty Cycle
45
55
%
Measured at 1.5V
ZO
AC Output Impedance
15
48MHz Clock Output (Lump Capacitance Test Load = 20pF) (continued)
CPU = 66.6MHz
Units
Parameter
Min.
Typ. Max.
Test Condition/Comments
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