参数资料
型号: RC7102
厂商: FAIRCHILD SEMICONDUCTOR CORP
元件分类: 时钟产生/分配
英文描述: 133.3 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
封装: SSOP-48
文件页数: 14/16页
文件大小: 72K
代理商: RC7102
PRODUCT SPECIFICATION
RC7102
7
Advanced
Infor
mation
Z0
AC Output Impedance
30
ohm
Average value during switching transition. Used for
determining series termination value.
IOAPIC Clock Output (Lump Capacitance Test Load = 20pF)
CPU = 66.6/
100MHz
Units
Parameter
Min.
Typ. Max.
Test Condition/Comments
f
Frequency, Actual
14.3818
MHz
Frequency generated by crystal oscillator.
tR
Output Rise Edge Rate
1
4
V/ns
Measured from 0.4V to 2.0V.
tF
Output Fall Edge Rate
1
4
V/ns
Measured from 2.0V to 0.4V.
tD
Duty Cycle
45
55
%
Measured on rising and falling edge at 1.25V.
fST
Frequency Stabilization
from Power-up
(cold start)
1.5
ms
Assumes full supply voltage reached within 1ms
from power-up.
Z0
AC Output Impedance
15
ohm
Average value during switching transition. Used for
determining series termination value.
REF0:1 Clock Output (Lump Capacitance Test Load = 20pF)
CPU = 66.6/
100MHz
Units
Parameter
Min.
Typ. Max.
Test Condition/Comments
f
Frequency, Actual
14.3818
MHz
Frequency generated by crystal oscillator.
tR
Output Rise Edge Rate
0.5
2
V/ns
Measured from 0.4V to 2.4V.
tF
Output Fall Edge Rate
0.5
2
V/ns
Measured from 2.4V to 0.4V.
tD
Duty Cycle
45%
55
%
Measured on rising and falling edge at 1.5V.
fST
Frequency Stabilization
from Power-up
(cold start)
3
ms
Assumes full supply voltage reached within 1ms
from power-up.
Z0
AC Output Impedance
40
ohm
Average value during switching transition. Used for
determining series termination value.
48MHz Clock Output (Lump Capacitance Test Load = 20pF)
CPU = 66.6MHz
Units
Parameter
Min.
Typ. Max.
Test Condition/Comments
f
Frequency, Actual
48.008
MHz
Determined by PLL divider ratio (see n/m below).
fD
Deviation from 48MHz
+167
ppm
(48.008 – 48)/48
m/n
PLL Ratio
57/17
(14.31818MHz x 57/17 = 48.008MHz)
tR
Output Rise Edge Rate
0.5
2
V/ns
Measured from 0.4V to 2.4V.
tF
Output Fall Edge Rate
0.5
2
V/ns
Measured from 2.4V to 0.4V.
tD
Duty Cycle
45%
55
%
Measured on rising and falling edge at 1.5V.
PCI Clock Outputs, PCI_F and PCI_1:5 (Lump Capacitance Test Load = 30pF) (continued)
CPU = 66.6/
100MHz
Units
Parameter
Min.
Typ. Max.
Test Condition/Comments
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