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参数资料
| 型号： | RC7102 |
| 厂商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 133.3 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封装： | SSOP-48 |
| 文件页数： | 4/16页 |
| 文件大小： | 72K |
| 代理商： | RC7102 |
RC7102
PRODUCT SPECIFICATION
12
Advanced
Infor
mation
Writing Data Bytes
Each bit in Data Bytes 0-5 control a particular device func-
tion except for the "reserved" bits which must be written as a
logic 0. Bits are written MSB (most signicant bit) rst,
which is bit 7. Table 5 gives the bit formats for registers
located in Data Bytes 0-5.
Table 6 details additional frequency selections that are avail-
able through the serial data interface.
Table 7 details the select functions for Byte 0, bits 1 and 0.
Table 5. Data Bytes 0-5 Serial Conguration Map
Bit(s)
Affected Pin
Control Function
Bit Control
Pin No.
Pin Name
0
1
Default
Data Byte 0
7
—
CPU and
PCI
Spread Amount - Must equal 1
for Down Spread
± 0.25
± 0.5
0
6
—
SEL_2
See Table 6
0
5
—
SEL_1
See Table 6
0
4
—
SEL_0
See Table 6
0
3
—
Hardware/Software Frequency
Select
Hardware
Software
0
2
—
CPU and
PCI
Spread Type
Center
Down
0
1
7, 8, 10, 11,
12, 13, 43, 44
CPU and
PCI
Spread Spectrum Clock
Normal
Spread
0
All Clocks
Clock Output Tristate
Active
Tristate
0
Data Byte 1
7
—
(Reserved)
—
1
6
—
(Reserved)
—
1
5
—
(Reserved)
—
1
4
—
Test Mode
see Table 7
1
3
40
SDRAM12
Clock Output Disable
Low
Active
1
2
41
SDRAM13
Clock Output Disable
Low
Active
1
43
CPU1
Clock Output Disable
Low
Active
1
0
44
CPU0
Clock Output Disable
Low
Active
1
Data Byte 2
7
—
(Reserved)
—
1
6
7
PCI_F
Clock Output Disable
Low
Active
1
5
—
(Reserved)
—
1
4
13
PCI5
Clock Output Disable
Low
Active
1
3
12
PCI4
Clock Output Disable
Low
Active
1
2
11
PCI3
Clock Output Disable
Low
Active
1
10
PCI2
Clock Output Disable
Low
Active
1
0
8
PCI1
Clock Output Disable
Low
Active
1
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