参数资料
型号: RM5261A-300H
厂商: PMC-SIERRA INC
元件分类: 微控制器/微处理器
英文描述: 64-BIT, 300 MHz, MICROPROCESSOR, PQFP208
封装: HEAT SPREADER, MQFP-208
文件页数: 14/42页
文件大小: 898K
代理商: RM5261A-300H
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
21
Document ID: PMC-2002240, Issue 1
RM5261A Microprocessor with 64-Bit System Bus Data Sheet
Preliminary
Table 3 Cache Attributes
3.20 Write buffer
Writes to external memory, whether cache miss write-backs or stores to uncached or write-through
addresses, use the on-chip write buffer. The write buffer holds up to four 64-bit address and data
pairs. The entire buffer is used for a data cache write-back and allows the processor to proceed in
parallel with the memory update. For uncached and write-through stores, the write buffer
significantly increases performance by decoupling the SysAD bus transfers from the instruction
execution stream.
3.21 System Interface
The system interface consists of a 64-bit Address/Data bus with 8 parity check bits and a 9-bit
command bus. In addition, there are 6 handshake signals and 6 interrupt inputs. The interface is
capable of transferring data between the processor and memory at a peak rate of 800MB/sec with a
100MHz SysClock.
Figure 6 shows a typical embedded system using the RM5261A. In this example, a bank of
DRAMs and a memory controller ASIC share the processor’s SysAD bus while the memory
controller provides separate ports to a boot ROM and an I/O system.
Characteristics
Instruction
Data
Size
32KB
Organization
2-way set associative
Line size
32B
Index
vAddr11..0
Tag
pAddr31..12
Write policy
n.a.
write-back/write-through
Read order
sub-block
Write order
sequential
miss restart after transfer of
entire line
first double
Parity
per-word
per-byte
Cache locking
set A
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