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参数资料
| 型号： | RM5261A-300H |
| 厂商： | PMC-SIERRA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 64-BIT, 300 MHz, MICROPROCESSOR, PQFP208 |
| 封装： | HEAT SPREADER, MQFP-208 |
| 文件页数： | 29/42页 |
| 文件大小： | 898K |
| 代理商： | RM5261A-300H |
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Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
35
Document ID: PMC-2002240, Issue 1
RM5261A Microprocessor with 64-Bit System Bus Data Sheet
Preliminary
9.3
System Interface Parameters1
9.4
Boot-Time Interface Parameters
Parameter1
Symbol Conditions
CPU Speed
Units
250 MHz to 350 MHz
Min
Max
Data Output2,3 tDO
mode14..13 = 105,6 (fastest)
1.0
5.0
ns
mode14..13 = 015,6 (slowest)
1.0
6.0
ns
Data Setup4
tDS
6
trise = see above table
tfall = see above table
2.5
ns
Data Hold4
tDH
1.0
ns
Notes
1.
Timings are measured from 0.425 x VccIO of clock to 0.425 x VccIO of signal for 3.3V I/O.
Timings are measured from 0.48 x VccIO of clock to 0.48 x VccIO of signal for 2.5V I/O.
2.
Capacitive load for all maximum output timings is 50 pF. Minimum output timings are for
theoretical no load condition-untested.
3.
Data Output timing applies to all signal pins whether tristate I/O or output only.
4.
Setup and Hold parameters apply to all signal pins whether tristate I/O or input only.
5.
Only mode 14:13 = 10 is tested and guaranteed.
6.
Data shown is for 3.3 V I/O. For 2.5 V I/O derate all times by .5 nS.
Parameter
Symbol
Min
Max
Units
Mode Data Setup
tDS
4
SysClock cycles
Mode Data Hold
tDH
0
SysClock cycles
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相关代理商/技术参数 |
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| RM5261A-300HI-B002 | 制造商:PMC Sierra from Components Direct 功能描述:MICROPROCESSOR 64-BIT 300MHZ 0.18UM TECHNOLOGY - Trays 制造商:PMC-Sierra 功能描述:PMC SIERRA RM5261A-300HI-B002, Microprocessor 64-Bit 300MHz 0.18um Technology 3.3V 208-Pin MQFP |
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