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参数资料
| 型号： | RM5261A-300H |
| 厂商： | PMC-SIERRA INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 64-BIT, 300 MHz, MICROPROCESSOR, PQFP208 |
| 封装： | HEAT SPREADER, MQFP-208 |
| 文件页数： | 5/42页 |
| 文件大小： | 898K |
| 代理商： | RM5261A-300H |
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Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
13
Document ID: PMC-2002240, Issue 1
RM5261A Microprocessor with 64-Bit System Bus Data Sheet
Preliminary
Table 1 Integer Multiply/Divide Operations
The baseline MIPS IV ISA specifies that the results of a multiply or divide operation be placed in
the Hi and Lo registers. These values can then be transferred to the general purpose register file
using the Move-from-Hi and Move-from-Lo (MFHI/MFLO) instructions.
In addition to the baseline MIPS IV integer multiply instructions, the RM5261A also implements
the 3-operand multiply instruction, MUL. This instruction specifies that the multiply result go
directly to the integer register file rather than the Lo register. The portion of the multiply that
would have normally gone into the Hi register is discarded. For applications where it is known that
the upper half of the multiply result is not required, using the MUL instruction eliminates the
necessity of executing an explicit MFLO instruction.
The multiply-add instructions, MAD and MADU, multiply two operands and add the resulting
product to the current contents of the Hi and Lo registers. The multiply-accumulate operation is
the core primitive of almost all signal processing algorithms, allowing the RM5261A to eliminate
the need for a separate DSP engine in many embedded applications.
3.8
Floating-Point Co-Processor
The RM5261A incorporates a high-performance fully pipelined floating-point co-processor which
includes a floating-point register file and autonomous execution units for multiply/add/convert and
divide/square root. The floating-point coprocessor is a tightly coupled execution unit, decoding
and executing instructions in parallel with, and in the case of floating-point loads and stores, in
cooperation with the integer unit. The superscalar capabilities of the RM5261A allow floating-
point computation instructions to issue concurrently with integer instructions.
3.9
Floating-Point Unit
The RM5261A floating-point execution unit supports single and double precision arithmetic, as
specified in the IEEE Standard 754. The execution unit is broken into a separate divide/square root
unit and a pipelined multiply/add unit. Overlap of the divide/square root and multiply/add
operations is supported.
The RM5261A maintains fully precise floating-point exceptions while allowing both overlapped
and pipelined operations. Precise exceptions are extremely important in object-oriented
programming environments and highly desirable for debugging in any environment.
Opcode
Operand
Size
Latency
Repeat
Rate
Stall
Cycles
MULT/U,
MAD/U
16 bit
3
2
0
32 bit
4
3
0
MUL
16 bit
3
2
1
32 bit
4
3
2
DMULT,
DMULTU
any
7
6
0
DIV, DIVD
any
36
0
DDIV,
DDIVU
any
68
0
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相关代理商/技术参数 |
参数描述 |
|---|---|
| RM5261A-300HI-B002 | 制造商:PMC Sierra from Components Direct 功能描述:MICROPROCESSOR 64-BIT 300MHZ 0.18UM TECHNOLOGY - Trays 制造商:PMC-Sierra 功能描述:PMC SIERRA RM5261A-300HI-B002, Microprocessor 64-Bit 300MHz 0.18um Technology 3.3V 208-Pin MQFP |
| RM5261A-300J-B002 | 制造商:PMC Sierra from Components Direct 功能描述:RM5261A-300J-B002, MICROPROCESSOR 64-BIT 300MHZ 0.18UM TECHN - Trays 制造商:PMC SIERRA 功能描述:PMC SIERRA RM5261A-300J-B002, Microprocessor 64-Bit 300MHz 0.18um Technology 3.3V 208-Pin LFMQFP |
| RM5270-150S | 制造商:未知厂家 制造商全称:未知厂家 功能描述:64-Bit Microprocessor |
| RM5270-200S | 制造商:未知厂家 制造商全称:未知厂家 功能描述:64-Bit Microprocessor |
| RM5271-200S | 制造商:未知厂家 制造商全称:未知厂家 功能描述:64-Bit Microprocessor |
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