参数资料
型号: RM5261A-300H
厂商: PMC-SIERRA INC
元件分类: 微控制器/微处理器
英文描述: 64-BIT, 300 MHz, MICROPROCESSOR, PQFP208
封装: HEAT SPREADER, MQFP-208
文件页数: 19/42页
文件大小: 898K
代理商: RM5261A-300H
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer’s Internal Use
26
Document ID: PMC-2002240, Issue 1
RM5261A Microprocessor with 64-Bit System Bus Data Sheet
Preliminary
3.32 Boot-Time Modes
The boot-time serial mode stream is defined in Table 4. Bit 0 is the bit presented to the processor
as the first bit in the stream when VccOK is asserted. Bit 255 is the last bit transferred.
Table 4 Boot-Time Mode Bit Stream
Mode
bit
Description
Mode
bit
Description
0
reserved (must be zero)
15
Reserved: Must be zero
4:1
Write-back data rate
0: DDDD
1: DDxDDx
2: DDxxDDxx
3: DxDxDxDx
4: DDxxxDDxxx
5: DDxxxxDDxxxx
6: DxxDxxDxxDxx
7: DDxxxxxxDDxxxxxx
8: DxxxDxxxDxxxDxxx
9-15 reserved
17:16
System configuration identifiers -
software visible in Config[21..20]
register
7:5
Pclock to SysClock Multiplier
Mode Bits 7:5
Mode Bit 20=0
Mode Bit 20=1
000
Multiply by 2
n/a
001
Multiply by 3
n/a
010
Multiply by 4
n/a
011
Multiply by 5
Multiply by 2.5
100
Multiply by 6
n/a
101
Multiply by 7
Multiply by 3.5
110
Multiply by 8
n/a
111
Multiply by 9
Multiply by 4.5
19:18
Reserved: Must be zero
8
Specifies byte ordering. Logically ORed with
BigEndian input signal.
0: Little endian
1: Big endian
20
Select Pclock to SysClock Multiply
Mode
0: Integer Multipliers
1: Half-Integer Multipliers
10:9
Non-Block Write Protocol
00: R4000 compatible
01: reserved
10: pipelined
11: write re-issue
21
External Bus Width
0: 64-bit
1: 32-bit
11
Timer Interrupt Enable/Disable
0: Enable the timer interrupt on Int5*
1: Disable the timer interrupt on Int5*
22
VccIO Setting
0: VccIO = 3.3V
1: VccIO = 2.5V
12
Reserved: Must be zero
255:23
Reserved: Must be zero
14:13
Output driver strength - 100% = fastest
00: 67% strength
01: 50% strength
10: 100% strength
11: 83% strength
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