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参数资料
| 型号： | RTC6581 |
| 元件分类： | 时钟/数据恢复及定时提取 |
| 英文描述： | REAL TIME CLOCK, PDIP24 |
| 封装： | DIP-24 |
| 文件页数： | 13/35页 |
| 文件大小： | 591K |
| 代理商： | RTC6581 |
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EPSON
EPSON ELECTRONICS AMERICA, INC.
RTC-658X/RTC-659X
5. IRQ Interrupts
The module includes three separate, fully automatic sources of IRQ interrupt for a processor. The alarm interrupt may
be programmed to occur at rates from once per second to once per day. The periodic interrupt may be selected for
rates of 500 ms to 122
s. The update-ended interrupt may be used to indicate to the processor that an update cycle
is complete. Each of these interrupt conditions is described in greater detail in the following sections.
(1) Enabling Interrupts
Three bits in Register B are used to select which source or sources of interrupt will be enabled. Setting the appropriate
interrupt-enable bit to 1 permits the interrupt to be initiated when the interrupt event occurs. A0 interrupt-enable bit
prohibits the IRQ pin from being asserted from that interrupt condition. If an interrupt flag is already set when an
interrupt is enabled, the IRQ pin is asserted immediately even though the event causing the interrupt may have
occurred much earlier. As a result, there are cases where the program should clear any pending interrupt conditions
before enabling new interrupts.
(2) Interrupt Status
Register C is used as an interrupt status register. Three flag bits correspond to the three interrupt sources. These
three bits are set respectively when the appropriate interrupt condition is satisfied regardless of the setting of interrupt
enable bits in register B. These flag bits can be used in a polling mode without enabling the corresponding interrupt
enable bits. When a flag bit is set in register C, this is an indication to the program that an interrupt event has occurred
since the register C has last been read. The act of reading register C clears all flag bits. Therefore all flag bits should
be examined by software upon each read of register C to insure that no interrupts are lost. Interrupt flags are double
buffered so that new interrupt event is held pending.
If an interrupt enable bit in register B is set and its corresponding interrupt flag in register C is also set, the IRQ bit is
asserted low. The IRQ bit is asserted low as long as at least one of the three interrupt sources has both its flag bit (in
register C) and its enable bit (in register B) set. The IRQF bit in register C will read logic as the IRQ pin is being driven
low. The microprocessor can determine if the real time clock module has initiated the interrupt by reading register C. A
logic one in the bit 7 position of register C indicates that one or more interrupts have been initiated by the real time
clock module. The act of reading register C clears all active flag bits and the IRQF bit.
(3) Periodic Interrupt
The periodic interrupt will cause the RTC module to generate an interrupt at time intervals ranging from 122
s to 500
ms. This function is separate from the alarm function which may generate interrupts at intervals of once per second to
once per day. The periodic interrupt rate is selected using the RS
0- RS3 bits in register A. Changing the RS bits affect
both the periodic interrupt rate and the square wave output rate.
(4) Update (Cycle) Ended Interrupt
The Update-In-Progress (UIP) bit in register A pulses once per second whenever an update cycle occurs. The Update
ended interrupt Flag (UF) will be set at conclusion of the update cycle or when the UIP bit in register A toggles from
logic 1 to logic 0. If the Update-ended Interrupt Enable (UIE) bit in Register B is also set, the IRQ pin will be asserted
low.
(5) Alarm Interrupt
The three alarm bytes may be used in two ways. First, when the alarm time is written in the appropriate locations, the
alarm interrupt is initiated at the specified time each day if the alarm enable bit is set to logic 1.
Second, it is used to insert a "don't care code" into one or more of the three alarms bytes. The "don't care code" is any
hexadecimal value from C0 to FF. The two most significant bits of each byte set the "don't care" condition when they
are set to logic 1. An alarm each hour occurs when “don’t care codes” is written in the hours alarm locations.
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PDF描述 |
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| RV5C387A-F | 0 TIMER(S), REAL TIME CLOCK, PDSO10 |
| RX-4571LC | REAL TIME CLOCK, PDSO12 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| RTC-6583 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Real-Time Clock |
| RTC-6587 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Real-Time Clock |
| RTC-6593 | 制造商:EPSON 制造商全称:EPSON 功能描述:REAL TIME CLOCK MODULE FOR PC/AT |
| RTC-6597 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Real-Time Clock |
| RTC6601 | 制造商:Richwave 功能描述:SP3T SWITCH, DFN 2x2-8L |
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