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| 型号： | RTC6581 |
| 元件分类： | 时钟/数据恢复及定时提取 |
| 英文描述： | REAL TIME CLOCK, PDIP24 |
| 封装： | DIP-24 |
| 文件页数： | 15/35页 |
| 文件大小： | 591K |
| 代理商： | RTC6581 |
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EPSON
EPSON ELECTRONICS AMERICA, INC.
RTC-658X/RTC-659X
9. Update Cycle
The RTC module executes an update cycle once per second. The primary purpose of the update cycle is to the
clock/calendar by one second and to compare the updated time to the two alarm times.
If the time matches the Real-Time-Clock alarm at the end of the update cycle, then the Alarm Flag (bit 5 of Register C)
is set. If Alarm Interrupt Enable (bit 5 of Register B) is set, an Interrupt Request is generated on the IRQ pin and the
IRQF (bit 7 of Register C) is also set.
If the time matches the extended alarm at the end of the update cycle, then the XAF bit is also set. If XAIE is set, an
extended alarm interrupt request is generated on the XIRQ pin. (For RTC-6591/6593/6597 only.)
At the end of every update cycle, the Update Flag (bit 4 of Register C) is set. If the Update ended Interrupt Enable (bit
4 of Register B) is set then an Interrupt Request is generated and the IRQF is set.
There are three methods that can be employed to accurately access time, date and calendar data from the real time
clock module. The first uses the update-ended interrupt. If this interrupt is enabled, an interrupt occurs after every
update cycle. Immediately following this interrupt, the processor has 998 ms in which to read time and date
information before the next update cycle. If the processor reads the time and date within this interval, no possibility
exists for reading inconsistent times and calendar data. As with all interrupts, the IRQF bit in Register C should be
cleared before leaving the interrupt service routine.
Using the second method for reading time and date, the processor polls the Update-In-Progress (UIP) bit in Register
A to determine if the update cycle is in progress. The UIP bit will pulse once each second. After the UIP bit goes to one,
the update transfer occurs 244
s later. If the UIP bit is 0, the processor has at least 244 s before the time/date data
will be updated. Therefore the system should insure that interrupts and DMA activity do not preclude reading the time
and date information within 244
s.
The third method uses the periodic interrupt to determine if an update cycle is in progress. The UIP bit in Register A is
pulsed high half way between two PF bit pulses in Register C. The processor should read time and date information
within the time interval of (Tpi/2)+TBUC
Periodic Interrupt And Update Ended Interrupt Relationship
Notes:
t pi = time interval for periodic interrupt according to Table 3
t UC = update cycle time = 1984
s
t BUC = delay before update cycle = 244
s
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PDF描述 |
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| RCPXA270C0C520 | 520 MHz, MICROPROCESSOR, PBGA356 |
| RV5C387A-F | 0 TIMER(S), REAL TIME CLOCK, PDSO10 |
| RX-4571LC | REAL TIME CLOCK, PDSO12 |
| RX-4571SA | REAL TIME CLOCK, PDSO14 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| RTC-6583 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Real-Time Clock |
| RTC-6587 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Real-Time Clock |
| RTC-6593 | 制造商:EPSON 制造商全称:EPSON 功能描述:REAL TIME CLOCK MODULE FOR PC/AT |
| RTC-6597 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Real-Time Clock |
| RTC6601 | 制造商:Richwave 功能描述:SP3T SWITCH, DFN 2x2-8L |
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