参数资料
型号: RTC6581
元件分类: 时钟/数据恢复及定时提取
英文描述: REAL TIME CLOCK, PDIP24
封装: DIP-24
文件页数: 16/35页
文件大小: 591K
代理商: RTC6581
EPSON
EPSON ELECTRONICS AMERICA, INC.
RTC-658X/RTC-659X
nRegisters
The Real Time Clock module has six control registers which are accessible at all times, even during update cycles.
1. Register A
MSB
LSB
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
UIP
DV2
DV1
DV0
RS3
RS2
RS1
RS0
(1)UIP:
The Update-In-Progress (UIP) bit is a status flag that can be monitored by the processor. When the UIP bit reads
logic 1, a single update transfer will occur. When the UIP reads 0, the update transfer will not occur for at least 244
s. The time, calendar, and alarm information in RAM is fully available for access when the UIP bit is 0. The UIP bit
is read only and is not affected by a reset. Setting the SET bit in register B to one aborts any update transfer and
clears the UIP status bit.
(2) DV0, DV1, DV2:
These three bits are used to turn the oscillator on or off and to reset the countdown chain. A pattern of 010 is the
only combination of bits that will turn on the oscillator and allow the RTC to keep time. A pattern of 11 X enables
the oscillator but holds the count down chain in reset. The oscillator becomes active after IRC, when the DV bits
are changed from 000. If the timing chain is held in reset with the oscillator running by writing a pattern of 11 X, the
first update transfer occurs 500 ms after writing a pattern of 010 to bits DV0, DV1, and DV2 respectively.
Oscillator control bits
DV2
DV1
DV0
Effect on Divider
0
Oscillator off.
1
×
Reset divider chain. Oscillator enabled.
0
1
0
Oscillator on. (Normal operation)
(3) RS3, RS2, RS1, RS0:
These four bits are used to select 1 of 13 frequencies on the 15-stage divider and to disable the divider output pin
signal. See table below. The selected frequencies may be used to generate an output square wave (on the SOW
pin and/or a periodic interrupt. The user may do one of the following:
1: Enable the interrupt with the PIE bit=”1", SQWE bit=”0"
2: Enable the SOW output pin with the SQWE bit=”1", PIE bit =”0"
3: Enable both PIE and SQWE bit with the PIE=SQWE=”1"
4: Not use both PIE and SQWE bit with the PIE=SQWE=”0"
Periodic Interrupt Rate And Square Wave Output Frequency
Register A Select Bits
RS3
RS2
RS1
RS0
Periodic
Interrupt Rate
SQW Output
Frequency
0
NONE
0
1
3.90625 mS
256 Hz
0
1
0
7.8125 mS
128 Hz
0
1
122.070
S
8.192 kHz
0
1
0
244.141
S
4.096 kHz
0
1
0
1
488.281
S
2.048 kHz
0
1
0
976.5625
S
1.024 kHz
0
1
1.953125 mS
512 Hz
1
0
3.90625 mS
256 Hz
1
0
1
7.8125 mS
128 Hz
1
0
1
0
15.625 mS
64 Hz
1
0
1
31.25 mS
32 Hz
1
0
62.5 mS
16 Hz
1
0
1
125.000 mS
8 Hz
1
0
250.000 mS
4 Hz
1
500.000 mS
2 Hz
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