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参数资料
| 型号： | RTC6581 |
| 元件分类： | 时钟/数据恢复及定时提取 |
| 英文描述： | REAL TIME CLOCK, PDIP24 |
| 封装： | DIP-24 |
| 文件页数： | 34/35页 |
| 文件大小： | 591K |
| 代理商： | RTC6581 |
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EPSON
EPSON ELECTRONICS AMERICA, INC.
RTC-658X/RTC-659X
2. Signal Descriptions
(1) VDD, VSS -- Power Supply
D.C. power is provided to the device on these pins. VDD is the +5V input. When VDD is applied within normal limits, the
device is fully accessible and data can be written and read. When VDD is below VENABLE, reads and writes are
inhibited. However, the timekeeping function continues unaffected by the lower input voltage. As VDD falls below
VSWITCH, the RAM and Real Time Clock are switched over to the power supply from the VBAT pin. The timekeeping
function maintains an accuracy of approximately 1-minute per month at 25
°C regardless of the voltage input on the
VDD pin.
(2) MOT -- Mode Select (input)
The MOT pin offers the flexibility to choose between two bus types. When connected to VDD, the Motorola bus timing
is selected. When connected to Vss or disconnected, the Intel bus timing is selected. The pin has an internal pull-down
resistance of approximately 20k
.
(3) AD
0-AD7 -- (Multiplexed Bi-Directional Address/Data Buses)
Multiplexed buses save pins because address information and data information time-share the same signal paths.
The address are presented during the first portion of the bus cycle and the same pins and signal paths are used for
data in the second portion of the cycle. Address/data multiplexing does not slow the access time of the Real Time
Clock since the bus change from address to data occurs during the internal RAM access time. Address must be valid
prior to the falling edge of AS or ALE, at which time the Real Time Clock latches the address from AD
0 to AD6. Valid
write data must be present and held stable during the latter portion of the DS or WR pulses. In a read cycle the Real
Time Clock outputs of 8 bits data during the latter portion of the RD or DS pulses. The read cycle is terminated and the
bus return to a high impedance state as DS transitions low in the case of Motorola timing or as RD transitions high in
the case of Intel timing.
(4) AS -- Address Strobe (input)
A positive going address strobe pulse serves to demultiplex the bus. The falling edge of AS/ALE causes the address
to be latched within the Real Time Clock.
(5) DS -- Data Strobe or Read Strobe (input)
The DS/RD pin has two modes of operation depending on the level of the MOT pin. When the MOT pin is connected
to VDD, Motorola bus timing is selected. In this mode DS is a positive pulse during the latter portion of the bus cycle
and is called Data Strobe. During read cycles, DS signifies the time that the module is to drive the bi-directional bus.
In write cycles the trailing edge of DS causes the module to latch the written data.
When the MOT pin is connected to Vss, Intel bus timing is selected. In this mode the DS pin is called Read (RD). RD
identifies the time period when the module drives the bus with read data. The RD signal is the same definition as the
Output Enable (OE) signal on a typical memory device.
(6) R/W - Read/Write (input)
The R/W pin also has two modes of operation. When the MOT pin is connected to VDD for Motorola timing, R/W is a
level, which indicates whether the current cycle is a read, or write. A high level on R/W indicates a read cycle while DS
is high. For write cycles, R/W is low while DS is high.
When the MOT pin is connected to Vss for Intel bus timing, the R/W signal is an active low signal called WR. In this
mode the R/W pin has the same meaning as the Write Enable signal (WE) on a generic RAM.
(7) RTC (CS) -- Real Time Clock Select (input)
The Real Time Clock Select signal must be asserted low for a bus cycle in which the Real Time Clock and RAM
module are to be accessed. RTC must be kept in the active state ("L") during DS and AS is High for Motorola timing
and during RD and WR is Low for Intel timing. Bus cycles, which take place without asserting RTC, will latch
addresses but no access will occur. When VDD is below VENABLE, the module internally inhibits access cycles by
internally disabling the RTC input. This action protects both the Real Time Clock data and RAM data during power
failures.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| RTC-6583 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Real-Time Clock |
| RTC-6587 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Real-Time Clock |
| RTC-6593 | 制造商:EPSON 制造商全称:EPSON 功能描述:REAL TIME CLOCK MODULE FOR PC/AT |
| RTC-6597 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Real-Time Clock |
| RTC6601 | 制造商:Richwave 功能描述:SP3T SWITCH, DFN 2x2-8L |
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