参数资料
型号: RTC6581
元件分类: 时钟/数据恢复及定时提取
英文描述: REAL TIME CLOCK, PDIP24
封装: DIP-24
文件页数: 14/35页
文件大小: 591K
代理商: RTC6581
EPSON
EPSON ELECTRONICS AMERICA, INC.
RTC-658X/RTC-659X
6. XIRQ Interrupt: (For RTC-6591/6593/6597 only)
The extended alarm functions provide the additional interrupt signal XIRQ. This is independent of the alarm functions
using the IRQ interrupt. The extended alarm interrupt may be programmed to occur at rates from once per second to
once per year. This interrupt may be used as a wake-up system for a main CPU.
This interrupt condition is described in greater detail in the following sections.
This interrupt is active even during battery backup.
(1) Enabling the extended alarm interrupt: (For RTC-6591/6593/6597 only)
The XAIE bit in register 6 of Extended alarm area indicates whether the interrupt is enabled. Writing 1 to the XAIE bit
permits the interrupt to occur when the extended alarm interrupt event occurs. A 0 in the XAIE bit prohibits the XIRQ
pin from being asserted from that interrupt condition. If an extended alarm interrupt flag is already set when an
interrupt is enabled, the XIRQ pin is asserted immediately even though the event causing the interrupt may have
occurred much earlier.
(2) Extended alarm interrupt Status: (For RTC-6591/6593/6597 only)
The XAF bit of register 7 of extended alarm area is used as an interrupt status register. This bit is set respectively
when the appropriate interrupt condition is satisfied regardless of the setting of XAIE bit in register 6. This flag bit can
be used in a polling mode without enabling the corresponding XAIE bit. When the XAF bit is set in register 7,this is an
indication to the program that an extended alarm interrupt event has occurred since the register 6 was fast read.
Interrupt flags are double buffered so that new interrupt event is held pending.
If the XAIE bit in register 6 is set and its corresponding interrupt flag in register 7 is also set, the XIRQ pin is asserted
low. The XIRQ pin is asserted low as long as at the extended alarm interrupt source has both its XAF bit and its XAIE
bit set. The microprocessor can determine if the RTC module has initiated the extended alarm interrupt by reading the
XAF bit in register 6. A one in the XAF bit indicates that the RTC module has initiated the extended alarm interrupt.
The act of reading register 7 clear the XAF bit.
(3) Extended alarm Interrupt: (For RTC-6591/6593/6597 only)
The six alarm bytes may be used in two ways. First, when the alarm time is written in the appropriate locations, the
alarm interrupt is initiated at the specified time each year if the XAIE bit is set to one. Second, it is used to insert a
"don't care code" into one or more of the six alarms bytes. The "don't care code" is any hexadecimal value from C0 to
FF. The two most significant bits of each byte set the "don't care" condition when they are set to logic one. An alarm
each hour occurs when “don’t care codes” is written in the hours, day-of-week, day and month alarm locations.
7. Oscillator Control Bits
When power is first supplied, the status of these bits is indeterminate. After the batteries are installed, a pattern of 000
should be written to the module to turn off the oscillator to prevent the battery power source from being used.
A pattern of 010 in bits 4 through 6 of register A will turn on the oscillator and enable the countdown chain. A pattern
of 11X will turn on the oscillator but will leave the countdown chain reset. Please refer Register A - (2) about DV
0 to
DV
2 bits as details.
8. Square Wave Output Selection
Thirteen of the fifteen-divider taps are made available to a 1 of 15 selector. The divider taps may be used for two
purposes: first, to generate a fixed frequency square wave output signal on the SOW pin; second, to generate
interrupts at a selected frequency. The RS
0-RS3 bits in register A establish the square wave output frequency and/or
interrupt rate. These frequencies are listed in Register A- (3). Once the frequency is selected, the SOW pin signal may
be enabled or disabled under program control using the Square Wave Enable (SQWE) bit in Register B.
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