参数资料
型号: RTC6581
元件分类: 时钟/数据恢复及定时提取
英文描述: REAL TIME CLOCK, PDIP24
封装: DIP-24
文件页数: 18/35页
文件大小: 591K
代理商: RTC6581
EPSON
EPSON ELECTRONICS AMERICA, INC.
RTC-658X/RTC-659X
(8) DSE (Daylight Saving Enable: Read / Write)
The Daylight Saving Enable (DSE) bit is a read/write bit which enables two special updates when the DSE bit is set to
1. On the first Sunday in April, the time increments from 1:59:59 am to 3:00:00 am. On the last Sunday in October when
the time first reaches 1:59:59 am, it changes to 1:00:00 am. These special updates do not occur when the DSE bit is 0.
This bit is a read/write bit that is not modified by RESET or internal functions of the RTC module.
3.
Register C
MSB
LSB
BIT7
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 0
IRQF
PF
AF
UF
0
(1) IRQF Bit (Interrupt Request Flag: read only)
The Interrupt Request Flag (IRQF) bit is set to one when 1 or more of the following conditions hold:
PF=PIE=1
AF=AIE=1
→ IRQF=1
UF=UIE=1
That is, lRQF = PF
PIE+AFAIE+UFUIE
The IRQF bit is cleared by hardware RESET. All flag bits and IRQF bit are cleared to 0 after reading Register C.
(2) PF (Periodic Interrupt Flag; Read Only)
The Periodic interrupt Flag (PF) is a read only bit which is set to one when an edge occurs on the selected tap of the
dividers. The RS3 through RS0 bits establish the periodic divide rate. The PF bit is set to one independent of the state of
the PIE bit. When both the PF and PIE bits are set to 1, the IRQ signal is asserted and the IRQF bit is set to 1. The PF
bit is cleared by hardware RESET or by a read of Register C.
(3) AF (Alarm Interrupt Flag: Read Only)
The Alarm interrupt Flag (AF) is set when the current time matches the alarm register time. If the AIE bit is also set to 1,
the IRQ pin is driven low and the IRQF bit is set to 1. The AF bit is cleared by hardware RESET or by a read of Register
C.
(4) UF (Update Ended Interrupt Flag: Read Only)
The Update ended interrupt Flag (UF) is set after each update cycle. If the UIE bit is also set to 1, the IRQ pin is driven
low and the IRQF bit is set to 1. The UF bit is cleared by hardware RESET or by a read of Register C.
(5) Bits 3 through 0 (Read Only)
The remaining bits in Register C are read only and will always read as 0.
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