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参数资料
| 型号： | RTC6581 |
| 元件分类： | 时钟/数据恢复及定时提取 |
| 英文描述： | REAL TIME CLOCK, PDIP24 |
| 封装： | DIP-24 |
| 文件页数： | 19/35页 |
| 文件大小： | 591K |
| 代理商： | RTC6581 |
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EPSON
EPSON ELECTRONICS AMERICA, INC.
RTC-658X/RTC-659X
4.
Register D
MSB
LSB
BIT7
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 0
VRT
0
(1) VRT (Valid RAM and Time: Read Only)
The VRT bit provides a check function to determine if the back-up power supply was maintained. After a return from
battery backup mode, the first value read reflects the state of the VBAT voltage during the back-up interval. When this
first value read is 1, the back up has functioned correctly, and the RAM contents are guaranteed. If this bit first reads as
0, the back-up power was not maintained throughout the back-up period, and therefore the contents of memory in the
device are not guaranteed. It will be necessary to re-initialize. At power up when VDD pin voltage is between 0 to
VSWITCH, the module will be powered from the battery. When the VDD voltage exceeds VSWITCH, the module is
switched from backup power to VDD power. At the same time, an artificial load of 1
A (TYP.) is switched to the backup
power.
The artificial load remains applied until the VDD voltage reaches VENABLE voltage. At this time the backup power
voltage is compared with a VCHECK reference value. The voltage comparator output is clocked into the VRT bit latch.
The artificial load is removed after the comparator output state has been latched. The RESET pin does not affect this
bit.
This bit will always read as "0”on the first read after a battery is installed and VDD is supplied. All subsequent reads will
indicate the state of the battery on the most recent VDD power on.
(2) Bits 6 through 0 (Read Only)
The remaining bits in Register D are read only and will always read as 0.
5. Register 6 in Extended Alarm locations (For RTC-6591/6593/6597 only)
MSB
LSB
BIT7
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 0
0
XAIE
(1) XAIE (Extended Alarm Interrupt Enable: Read/Write)
The Extended Alarm Interrupt Enable (XAIE) bit is a read/write bit, which when set to 1, permits the Extended Alarm
Flag (XAF) bit in same Register to assert the XIRQ signal. An extended alarm interrupt occurs for each second that the
six extended alarm bytes (including the don't care alarm codes) equal the six time and calendar bytes. When the XAIE
bit is set to 0, the XAF bit does not assert the XIRQ signal. The XAIE bit is not modified by any internal RTC module
functions or hardware RESET signal.
(2) Bits 7 through 1 (Read Only)
The remaining bits in extended alarm register 6 are read only and will always read as 0.
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| RV5C387A-F | 0 TIMER(S), REAL TIME CLOCK, PDSO10 |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| RTC-6583 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Real-Time Clock |
| RTC-6587 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Real-Time Clock |
| RTC-6593 | 制造商:EPSON 制造商全称:EPSON 功能描述:REAL TIME CLOCK MODULE FOR PC/AT |
| RTC-6597 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Real-Time Clock |
| RTC6601 | 制造商:Richwave 功能描述:SP3T SWITCH, DFN 2x2-8L |
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