参数资料
型号: RTPXA270C5C520
厂商: INTEL CORP
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 520 MHz, RISC PROCESSOR, PBGA356
封装: 13 X 13 MM, 1.0MM PITCH, LEAD FREE, VFBGA-356
文件页数: 25/44页
文件大小: 1302K
代理商: RTPXA270C5C520
Electrical Specifications
Intel PXA255 Processor Electrical, Mechanical, and Thermal Specification
31
Note: If hardware reset is entered during sleep mode, follow the proper power-supply stabilization times
indicated in Figure 3 and nRESET timing requirements indicated in Table 15.
Figure 3. Power-On Reset Timing
Table 15. Power-On Timing Specifications
Symbol
Description
Min
Typical
Max
Units
tR_VCCQ
VCCQ rise / stabilization time
0.01
100
ms
tR_VCCN
VCCN rise / stabilization time
0.01
100
ms
tR_VCC
VCC, PLL_VCC rise / stabilization time
0.01
10
ms
tD_VCCN
Delay between VCCQ applied and
VCCN applied
0
ms
tD_VCC
Delay from VCCN applied and VCC,
PLL_VCC applied
-10
ms
tD_NTRST
Delay between VCC, PLL_VCC stable
and nTRST de-asserted
10
ms
tD_JTAG
Delay between nTRST de-asserted and
JTAG pins active, with nRESET
asserted
0.03
ms
tD_NRESET
Delay between VCC, PLL_VCC stable
and nRESET de-asserted
10
ms
tD_OUT
Delay between nRESET de-asserted
and nRESET_OUT de--asserted
18.1
18.2
ms
tD_NCS0
Delay between nRESET_OUT
deasserted and nCS0 asserted
400
420
ns
VCCQ, PWR_EN
VCC
nTRST
JTAG PINS
nRESET
nRESET_OUT
tR_VCCQ
tR_VCC
tD_NTRST
tD_JTAG
tD_NRESET
tD_OUT
VCCN
tR_VCCN
tD_VCC
tD_VCCN
NOTES:
1. nBATT_FAULT and nVDD_FAULT must be high before nRESET_OUT is deasserted or the
processor enters sleep mode.
2. The inclusion of PWR_EN is for informational purposes only to show its relationship to VCCQ. The
use of PWR_EN to bring up VCCN or VCC at power-on reset is optional depending on the system’s
power management requirements. VCCN and VCC are not dependant on the PWR_EN signal being
asserted.
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