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参数资料
| 型号： | RTPXA270C5C520 |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 520 MHz, RISC PROCESSOR, PBGA356 |
| 封装： | 13 X 13 MM, 1.0MM PITCH, LEAD FREE, VFBGA-356 |
| 文件页数： | 7/44页 |
| 文件大小： | 1302K |
| 代理商： | RTPXA270C5C520 |
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Package Information
Intel PXA255 Processor Electrical, Mechanical, and Thermal Specification
15
AC97 Controller and I2S Controller Pins
BITCLK/
GPIO[28]
ICOCZ
AC97 audio port bit clock. (input) AC97 clock is
generated by Codec 0 and fed into the PXA255
processor processor and Codec 1.
AC97 Aaudio port bit clock. (output) AC97 clock is
generated by the PXA255 processor.
I2S bit clock. (input) I2S clock is generated externally
and fed into PXA255 processor.
I2S bit clock. (output) I2S clock is generated by the
PXA255 processor.
Pulled High -
Note[1]
Note [3]
SDATA_IN0/
GPIO[29]
ICOCZ
AC97 audio port data in. (input) Input line for Codec 0.
I2S data in. (input) Input line for the I2S controller.
Pulled High -
Note[1]
Note [3]
SDATA_IN1/
GPIO[32]
ICOCZ
AC97 audio port data in. (input) Input line for Codec 1.
I2S system clock. (output) System clock from I2S
controller.
Pulled High -
Note[1]
Note [3]
SDATA_OUT/
GPIO[30]
ICOCZ
AC97 audio port data out. (output) Output from the
PXA255 processor to Codecs 0 and 1.
I2S data out. (output) Output line for the I2S controller.
Pulled High -
Note[1]
Note [3]
SYNC/
GPIO[31]
ICOCZ
AC97 audio port sync signal. (output) Frame sync
signal for the AC97 controller.
I2S sync. (output) Frame sync signal for the I2S
controller.
Pulled High -
Note[1]
Note [3]
nACRESET
OC
AC97 audio port reset signal. (output)
Driven Low
I2C Controller Pins
SCL
ICOCZ
I2C clock. (bidirectional)
Hi-Z
SDA
ICOCZ
I2C data. (bidirectional).
Hi-Z
PWM Pins
PWM[1:0]/
GPIO[17:16]
ICOCZ
Pulse width modulation channels 0 and 1. (outputs)
Pulled High -
Note[1]
Note [3]
DMA Pins
DREQ[1:0]/
GPIO[19:20]
ICOCZ
DMA request. (input) Notifies the DMA Controller that an
external device requires a DMA transaction. DREQ[1] is
GPIO[19]. DREQ[0] is GPIO[20].
Pulled High -
Note[1]
Note [3]
GPIO Pins
GPIO[1:0]
ICOCZ
General purpose I/O. Wakeup sources on both rising
and falling edges on nRESET.
Pulled High -
Note[1]
Note [3]
GPIO[14:2]
ICOCZ
General purpose I/O. More wakeup sources for sleep
mode.
Pulled High -
Note[1]
Note [3]
GPIO[22:21]
ICOCZ
General purpose I/O. Additional General Purpose I/O
pins.
Pulled High -
Note[1]
Note [3]
Crystal and Clock Pins
PXTAL
OA
3.6864 MHz crystal input. No external caps are
required.
Note [2]
PEXTAL
IA
3.6864 MHz crystal output. No external caps are
required.
Note [2]
TXTAL
OA
32 KHz crystal input. No external caps are required.
Note [2]
Table 3. Pin and Signal Descriptions for the PXA255 Processor (Sheet 7 of 9)
Pin Name
Type
Signal Descriptions
Reset State
Sleep State
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相关代理商/技术参数 |
参数描述 |
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| RTPXA270C5C624 | 功能描述:IC MPU 32BIT 624MHZ 356-PBGA RoHS:是 类别:集成电路 (IC) >> 嵌入式 - 微处理器 系列:- 标准包装:1 系列:MPC85xx 处理器类型:32-位 MPC85xx PowerQUICC III 特点:- 速度:1.2GHz 电压:1.1V 安装类型:表面贴装 封装/外壳:783-BBGA，FCBGA 供应商设备封装:783-FCPBGA（29x29） 包装:托盘 |
| RTPXA320B1C624-180 | 制造商:Marvell 功能描述:MONAHANS P 624MHZ - Trays |
| RTPXA320B1C624-203 | 制造商:Marvell 功能描述:MONAHANS P 624MHZ - Trays |
| RTPXA320B1C624-208 | 制造商:Marvell 功能描述:MONAHANS P 624MHZ - Trays |
| RTPXA320B1C624-209 | 制造商:Marvell 功能描述:MONAHANS P 624MHZ - Trays |
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