参数资料
型号: RTPXA270C5C520
厂商: INTEL CORP
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 520 MHz, RISC PROCESSOR, PBGA356
封装: 13 X 13 MM, 1.0MM PITCH, LEAD FREE, VFBGA-356
文件页数: 4/44页
文件大小: 1302K
代理商: RTPXA270C5C520
Package Information
12
Intel PXA255 Processor Electrical, Mechanical, and Thermal Specification
L_DD[9]/
GPIO[67]
ICOCZ
LCD display data. (output) Transfers pixel information
from the LCD controller to the external LCD panel.
MMC chip select 0. (output) Chip select 0 for the MMC
controller.
Pulled High -
Note[1]
Note [3]
L_DD[10]/
GPIO[68]
ICOCZ
LCD display data. (output) Transfers pixel information
from the LCD controller to the external LCD panel.
MMC chip select 1. (output) Chip select 1 for the MMC
controller.
Pulled High -
Note[1]
Note [3]
L_DD[11]/
GPIO[69]
ICOCZ
LCD display data. (output) Transfers pixel information
from the LCD controller to the external LCD panel.
MMC clock. (output) Clock for the MMC controller.
Pulled High -
Note[1]
Note [3]
L_DD[12]/
GPIO[70]
ICOCZ
LCD display data. (output) Transfers pixel information
from the LCD controller to the external LCD panel.
RTC clock. (output) Real-time clock 1 Hz tick.
Pulled High -
Note[1]
Note [3]
L_DD[13]/
GPIO[71]
ICOCZ
LCD display data. (output) Transfers pixel information
from the LCD controller to the external LCD panel.
3.6864 MHz clock. (output) Output from 3.6864 MHz
oscillator.
Pulled High -
Note[1]
Note [3]
L_DD[14]/
GPIO[72]
ICOCZ
LCD display data. (output) Transfers pixel information
from the LCD controller to the external LCD panel.
32 kHz clock. (output) Output from the 32 kHz oscillator.
Pulled High -
Note[1]
Note [3]
L_DD[15]/
GPIO[73]
ICOCZ
LCD display data. (output) Transfers pixel information
from the LCD controller to the external LCD panel.
Memory Controller grant. (output) Notifies an external
device it has been granted the system bus.
Pulled High -
Note[1]
Note [3]
L_FCLK/
GPIO[74]
ICOCZ
LCD frame clock. (output) Indicates the start of a new
frame. Also referred to as Vsync.
Pulled High -
Note[1]
Note [3]
L_LCLK/
GPIO[75]
ICOCZ
LCD line clock. (output) Indicates the start of a new line.
Also referred to as Hsync.
Pulled High -
Note[1]
Note [3]
L_PCLK/
GPIO[76]
ICOCZ
LCD pixel clock. (output) Clocks valid pixel data into the
LCD line-shift buffer.
Pulled High -
Note[1]
Note [3]
L_BIAS/
GPIO[77]
ICOCZ
AC bias drive. (output) Notifies the panel to change the
polarity for some passive LCD panel. For TFT panels,
this signal indicates valid pixel data.
Pulled High -
Note[1]
Note [3]
Full Function UART Pins
FFRXD/
GPIO[34]
ICOCZ
Full function UART receive. (input)
MMC chip select 0. (output) Chip select 0 for the MMC
Controller.
Pulled High -
Note[1]
Note [3]
FFTXD/
GPIO[39]
ICOCZ
Full Function UART transmit. (output)
MMC chip select 1. (output) Chip select 1 for the MMC
Controller.
Pulled High -
Note[1]
Note [3]
FFCTS/
GPIO[35]
ICOCZ
Full function UART clear-to-send. (input)
Pulled High -
Note[1]
Note [3]
FFDCD/
GPIO[36]
ICOCZ
Full function UART data-carrier-detect. (input)
Pulled High -
Note[1]
Note [3]
FFDSR/
GPIO[37]
ICOCZ
Full function UART data-set-ready. (input)
Pulled High -
Note[1]
Note [3]
Table 3. Pin and Signal Descriptions for the PXA255 Processor (Sheet 4 of 9)
Pin Name
Type
Signal Descriptions
Reset State
Sleep State
相关PDF资料
PDF描述
RCPXA272FC0520 520 MHz, MICROPROCESSOR, PBGA336
RCPXA273FC0416 416 MHz, MICROPROCESSOR, PBGA336
RCPXA273FC0520 520 MHz, MICROPROCESSOR, PBGA336
RCPXA272FC0312 312 MHz, MICROPROCESSOR, PBGA336
RCPXA271FC0312 312 MHz, MICROPROCESSOR, PBGA336
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