21 I2C Slave (I2CS)
21-18
Seiko Epson Corporation
S1C17601 TECHNICAL MANUAL
D4
BFREQ_EN: Bus Free Request Enable Bit
Enables/disables I2C bus free requests by inputting a low pulse to the #BFR pin.
1 (R/W): Enable
0 (R/W): Disable (default)
To accept I2C bus free requests, set BFREQ_EN to 1. When a bus free request is accepted, BFREQ
(D4/I2CS_STAT register) is set to 1. This initializes the I2C slave communication process and puts the
SDA1 and SCL1 pins into high-impedance state. The control registers will not be initialized in this
process.
When BFREQ_EN is set to 0, low pulse inputs to the #BFR pin are ignored and BFREQ is not set to 1.
D3
CLKSTR_EN: Clock Stretch On/Off Bit
Turns the clock stretch function on or off.
1 (R/W): On
0 (R/W): Off (default)
After data and ACK are transmitted or received, the slave device may issue a wait request to the master
device until it is ready to transmit/receive by pulling the SCL1 line down to low. The I2C slave module
supports this clock stretch function. The master device enters a standby state until the wait request is
canceled (the SCL1 input goes high). When using the clock stretch function, set CLKSTR_EN to 1
before starting data communication.
D2
NF_EN: Noise Filter On/Off Bit
Turns the noise filter on or off.
1 (R/W): On
0 (R/W): Off (default)
The I2C slave module contains a function to remove noise from the SDA1 and SCL1 input signals. This
function is enabled by setting NF_EN to 1.
D1
ASDET_EN: Async. Address Detection On/Off Bit
Turns the asynchronous address detection function on or off.
1 (R/W): On
0 (R/W): Off (default)
The I2C slave module operation clock (PCLK) frequency must be set eight-times or higher than the
transfer rate during data transfer. However, the PCLK frequency can be lowered to reduce current
consumption if no other processing is required during standby for data transfer. The asynchronous
address detection function is provided to detect the I2C slave address sent from the master in this status.
This function is enabled by setting ASDET_EN to 1. If the slave address sent from the master has
matched with one that has been set in this I2C slave module when the asynchronous address detection
function has been enabled, the I2C slave module generates a bus status interrupt and returns NAK to
the I2C master to request for resending the slave address. Set the PCLK frequency to eight-times or
higher than the transfer rate and reset ASDET_EN to 0 in the interrupt handler routine. Data transfer
will be able to resume normally after the master retries transmission. After the master generates a STOP
condition to put the I2C bus into free status, the asynchronous address detection function can be enabled
again to lower the operating speed.
Notes: When the asynchronous address detection function is enabled, the I2C signals are input
without passing through the noise filter. Therefore, the slave address may not be detected
in a high-noise environment.
When the asynchronous address detection function is enabled, data transfer cannot be
performed even if the PCLK frequency is eight-times or higher than the transfer rate. Be
sure to disable the asynchronous address detection function during normal operation.