Appendix A: I/O Register List
S1C17601 TECHNICAL MANUAL
Seiko Epson Corporation
AP-17
0x5060–0x5067
Oscillator
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
Clock Source
Select Register
(OSC_SRC)
0x5060
(8 bits)
D7–2 –
reserved
–
0 when being read.
D1
HSCLKSEL High-speed clock select
1 OSC3
0 IOSC
0
R/W
D0
CLKSRC
System clock source select
1 OSC1
0 HSCLK
0
R/W
Oscillation
Control Register
(OSC_CTL)
0x5061
(8 bits)
D7–6 IOSCWT[1:0] IOSC wait cycle select
IOSCWT[1:0]
Wait cycle
0x0 R/W
0x3
0x2
0x1
0x0
8 cycles
16 cycles
32 cycles
64 cycles
D5–4 OSC3WT[1:0] OSC3 wait cycle select
OSC3WT[1:0]
Wait cycle
0x0 R/W
0x3
0x2
0x1
0x0
128 cycles
256 cycles
512 cycles
1024 cycles
D3
–
reserved
–
0 when being read.
D2
IOSCEN
IOSC enable
1 Enable
0 Disable
1
R/W
D1
OSC1EN
OSC1 enable
1 Enable
0 Disable
0
R/W
D0
OSC3EN
OSC3 enable
1 Enable
0 Disable
0
R/W
Noise Filter
Enable Register
(OSC_NFEN)
0x5062
(8 bits)
D7–2 –
reserved
–
0 when being read.
D1
RSTFE
Reset noise filter enable
1 Enable
0 Disable
1
R/W
D0
NMIFE
NMI noise filter enable
1 Enable
0 Disable
0
R/W
LCD Clock
Setup Register
(OSC_LCLK)
0x5063
(8 bits)
D7–5 –
reserved
–
0 when being read.
D4–2 LCKDV[2:0] LCD clock division ratio select
LCKDV[2:0]
Division ratio
0x0 R/W Note: LCKDV and
LCKSRC must be
operated while
LCKEN is disabled.
0x7–0x5
0x4
0x3
0x2
0x1
0x0
reserved
HSCLK1/512
HSCLK1/256
HSCLK1/128
HSCLK1/64
HSCLK1/32
D1
LCKSRC
LCD clock source select
1 OSC1
0 HSCLK
1
R/W
D0
LCKEN
LCD clock enable
1 Enable
0 Disable
0
R/W
FOUT Control
Register
(OSC_FOUT)
0x5064
(8 bits)
D7–4 –
reserved
–
0 when being read.
D3–2 FOUTHD
[1:0]
FOUTH clock division ratio select
FOUTHD[1:0]
Division ratio
0x0 R/W Note: FOUTHD
must be operated
while FOUT1E
and FOUT1E are
disabled.
0x3
0x2
0x1
0x0
reserved
HSCLK1/4
HSCLK1/2
HSCLK1/1
D1
FOUTHE
FOUTH output enable
1 Enable
0 Disable
0
R/W
D0
FOUT1E
FOUT1 output enable
1 Enable
0 Disable
0
R/W
T8OSC1 Clock
Control Register
(OSC_T8OSC1)
0x5065
(8 bits)
D7–4 –
reserved
–
0 when being read.
D3–1 T8O1CK[2:0] T8OSC1 clock division ratio select T8O1CK[2:0]
Division ratio
0x0 R/W Note: T8O1CK must
be operated while
T8O1CE is disabled.
0x7–0x6
0x5
0x4
0x3
0x2
0x1
0x0
reserved
OSC11/32
OSC11/16
OSC11/8
OSC11/4
OSC11/2
OSC11/1
D0
T8O1CE
T8OSC1 clock output enable
1 Enable
0 Disable
0
R/W
SVD Clock
setup Register
(OSC_SVD)
0x5066
(8 bits)
D7–2 –
reserved
–
0 when being read.
D1
SVDSRC
SVD clock source select
1 OSC1
0 HSCLK1/512
1
R/W Note: SVDSRC must
be operated while
SVDEN is disabled.
D0
SVDCKEN SVD clock enable
1 Enable
0 Disable
0
R/W
RFC Clock
Setup Register
(OSC_RFC)
0x5067
(8 bits)
D7–2 –
reserved
–
0 when being read.
D3–2 RFTCKDV
[1:0]
RFC clock division ratio select
RFCDV[2:0]
Division ratio
0
R/W Note: RFCDV and
RFCSRC must
be operated while
RFCEN is disabled.
0x3
0x2
0x1
0x0
HSCLK1/8
HSCLK1/4
HSCLK1/2
HSCLK1/1
D1
RFTCKSRC RFC clock source select
1 OSC1
0 HSCLK
1
R/W
D0
RFTCKEN RFC clock enable
1 Enable
0 Disable
0
R/W