7 Oscillator Circuit (OSC)
7-16
Seiko Epson Corporation
S1C17601 TECHNICAL MANUAL
0x5061: Oscillation Control Register (OSC_CTL)
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
Oscillation
Control Register
(OSC_CTL)
0x5061
(8 bits)
D7–6
IOSCWT[1:0] IOSC wait cycle select
IOSCWT[1:0]
Wait cycle
0x0 R/W
0x3
0x2
0x1
0x0
8 cycles
16 cycles
32 cycles
64 cycles
D5–4
OSC3WT[1:0] OSC3 wait cycle select
OSC3WT[1:0]
Wait cycle
0x0 R/W
0x3
0x2
0x1
0x0
128 cycles
256 cycles
512 cycles
1024 cycles
D3
–
reserved
–
0 when being read.
D2
IOSCEN
IOSC enable
1 Enable
0 Disable
1
R/W
D1
OSC1EN
OSC1 enable
1 Enable
0 Disable
0
R/W
D0
OSC3EN
OSC3 enable
1 Enable
0 Disable
0
R/W
D[7:6]
IOSCWT[1:0]: IOSC Wait Cycle Select Bits
An oscillation stabilization wait time is set to prevent malfunctions due to unstable clock operations
when IOSC oscillation begins.
The IOSC clock is not fed to the system immediately after IOSC oscillation starts—e.g., when power is
first turned on, when waking from SLEEP, or the IOSC oscillation circuit is switched on via software,
until the time set here has elapsed.
Table 7.12.2: IOSC oscillation stabilization wait time settings
IOSCWT[1:0]
Oscillation stabilization wait time
0x3
8 cycles
0x2
16 cycles
0x1
32 cycles
0x0
64 cycles
(Default: 0x0)
Since this is set to 64 cycles (IOSC clock) after initial resetting, the CPU does not begin operating
immediately after resetting until this time has elapsed.
D[5:4]
OSC3WT[1:0]: OSC3 Wait Cycle Select Bits
An oscillation stabilization wait timer is set to prevent malfunctions due to unstable clock operation at
the start of OSC3 oscillation.
The OSC3 clock is not fed to the system immediately after OSC3 oscillation starts—for example, when
power is first turned on, on awaking from SLEEP, or when the OSC3 oscillation circuit is turned on via
software—until the time set here has elapsed.
Table 7.12.3: OSC3 oscillation stabilization wait time settings
OSC3WT[1:0]
Oscillation stabilization wait time
0x3
128 cycles
0x2
256 cycles
0x1
512 cycles
0x0
1,024 cycles
(Default: 0x0)
This is set to 1,024 cycles (OSC3 clock) after initial resetting. The CPU does not begin operating
immediately after resetting until this time has elapsed.
Note: The OSC3 oscillation start time depends on the oscillator and externally connected components.
The time should be set with an adequate oscillation stabilization wait time. Refer to the typical
oscillation start times specified in “28 Electrical Characteristics.”
D3
Reserved