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Appendix A: I/O Register List
S1C17601 TECHNICAL MANUAL
Seiko Epson Corporation
AP-9
0x4246–0x4268
16-bit Timer
Register name Address
Bit
Name
Function
Setting
Init. R/W
Remarks
16-bit Timer
Ch.1 Control
Register
(T16_CTL1)
0x4246
(16 bits)
D15–11 –
reserved
–
0 when being read.
D10
CKACTV
External clock active level select
1 High
0 Low
1
R/W
D9–8 CKSL[1:0] Input clock and pulse width
measurement mode select
CKSL[1:0]
Mode
0x0 R/W
0x3
0x2
0x1
0x0
reserved
Pulse width
External clock
Internal clock
D7–5 –
reserved
–
0 when being read.
D4
TRMD
Count mode select
1 One shot
0 Repeat
0
R/W
D3–2 –
reserved
–
0 when being read.
D1
PRESER
Timer reset
1 Reset
0 Ignored
0
W
D0
PRUN
Timer run/stop control
1 Run
0 Stop
0
R/W
16-bit Timer
Ch.1 Interrupt
Control Register
(T16_INT1)
0x4248
(16 bits)
D15–9 –
reserved
–
0 when being read.
D8
T16IE
16-bit timer interrupt enable
1 Enable
0 Disable
0
R/W
D7–1 –
reserved
–
0 when being read.
D0
T16IF
16-bit timer interrupt flag
1 Cause of
interrupt
occurred
0 Cause of
interrupt not
occurred
0
R/W Reset by writing 1.
16-bit Timer
Ch.2 Input
Clock Select
Register
(T16_CLK2)
0x4260
(16 bits)
D15–4 –
reserved
–
0 when being read.
D3–0 DF[3:0]
Timer input clock select
(Prescaler output clock)
DF[3:0]
Clock
0x0 R/W
0xf
0xe
0xd
0xc
0xb
0xa
0x9
0x8
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
reserved
PCLK1/16384
PCLK1/8192
PCLK1/4096
PCLK1/2048
PCLK1/1024
PCLK1/512
PCLK1/256
PCLK1/128
PCLK1/64
PCLK1/32
PCLK1/16
PCLK1/8
PCLK1/4
PCLK1/2
PCLK1/1
16-bit Timer
Ch.2 Reload
Data Register
(T16_TR2)
0x4262
(16 bits)
D15–0 TR[15:0]
16-bit timer reload data
TR15 = MSB
TR0 = LSB
0x0 to 0xffff
0x0 R/W
16-bit Timer
Ch.2 Counter
Data Register
(T16_TC2)
0x4264
(16 bits)
D15–0 TC[15:0]
16-bit timer counter data
TC15 = MSB
TC0 = LSB
0x0 to 0xffff
0xffff
R
16-bit Timer
Ch.2 Control
Register
(T16_CTL2)
0x4266
(16 bits)
D15–11 –
reserved
–
0 when being read.
D10
CKACTV
External clock active level select
1 High
0 Low
1
R/W
D9–8 CKSL[1:0] Input clock and pulse width
measurement mode select
CKSL[1:0]
Mode
0x0 R/W
0x3
0x2
0x1
0x0
reserved
Pulse width
External clock
Internal clock
D7–5 –
reserved
–
0 when being read.
D4
TRMD
Count mode select
1 One shot
0 Repeat
0
R/W
D3–2 –
reserved
–
0 when being read.
D1
PRESER
Timer reset
1 Reset
0 Ignored
0
W
D0
PRUN
Timer run/stop control
1 Run
0 Stop
0
R/W
16-bit Timer
Ch.2 Interrupt
Control Register
(T16_INT2)
0x4268
(16 bits)
D15–9 –
reserved
–
0 when being read.
D8
T16IE
16-bit timer interrupt enable
1 Enable
0 Disable
0
R/W
D7–1 –
reserved
–
0 when being read.
D0
T16IF
16-bit timer interrupt flag
1 Cause of
interrupt
occurred
0 Cause of
interrupt not
occurred
0
R/W Reset by writing 1.