7 Oscillator Circuit (OSC)
7-24
Seiko Epson Corporation
S1C17601 TECHNICAL MANUAL
7.13 Precautions
The oscillation start time depends on the oscillator and externally connected components. The time should be set
with an adequate OSC3 oscillation stabilization wait time. Refer to the typical oscillation start times specified in
“28 Electrical Characteristics.”
Switching the system clock from HSCLK to OSC1 immediately after starting OSC1 oscillation will stop the
system clock until the OSC1 clock starts up (for the OSC1 clock 256-cycle period).
The IOSC oscillator circuit cannot be stopped if the IOSC clock is being used as the system clock.
The OSC3 oscillator circuit cannot be stopped if the OSC3 clock is being used as the system clock.
The OSC1 oscillator circuit cannot be stopped if the OSC1 clock is being used as the system clock.
Since the FOUTH/FOUT1 signal is asynchronized with FOUTHE/FOUT1E writing, switching output on or off
will generate certain hazards.
Continuous access of write and read to CLKSRC register (D0/0x5060) is prohibited. Enter at least one instruction
that is not related to access to CLKSRC register between write and read.
Change of clock source selection (LCKSRC (D1/0x5063)) and clock division ratio selection (LCKDV
[2:0](D[4:]/0x5063)) should be executed when LCKEN(D0/0x5063) is 0 and the clock to LCD driver is in “Stop”
state.
Change of clock division ratio selection (T8O1CK [2:0](D[3:1]/0x5063)) should be executed when T8O1CE(D0/
0x5065) is 0 and the clock to 8-bit OSC1 timer is in “Stop” state.
Change of clock selection (SVDSRC (D1/0x5066)) should be executed when SVDCKEN (D0/0x5066)is 0 and
the clock to SVD is in “Stop” state.
Change of master clock selection (RFTCKSRC (D1/0x5067)) and clock division ratio selection (RFTCKDV
[1:0](D[3:2]/0x5067)) should be executed when RFTCKEN (D0/0x5067) is 0 and clock to RFC is in “Stop”
state.
Change of the single selection (FOUTHD [1:0] (D[3:2]/0x5064) of FOUTH clock frequency should be executed
when FOUTHE (D1/0x5064) is 0 and clock output is in “Stop” status.
The stability of oscillation depends on the oscillator and external add-on components. Full evaluation is required
for configuring shorter stabilization wait time.
OSC3 clock system supply wait time =< OSC3 oscillation start time (max.) + OSC3 oscillation stabilization wait
time.
Set OSC3EN (the D0/OSC_CTL register) to 0 while the OSC3 and OSC4 pins are kept open.
Set OSC1EN (the D1/OSC_CTL register) to 0 while the OSC1 and OSC2 pins are kept open.