6 Interrupt Controller
6-2
Seiko Epson Corporation
S1C17601 TECHNICAL MANUAL
6.2 Vector Table
The vector table contains the vectors (processing routine start addresses) for interrupt processing routines. When
an interrupt occurs, the S1C17 core reads the vector corresponding to the interrupt and executes that processing
routine. The base (top) address for the vector table can be set using the MISC_TTBRL and MISC_TTBRH registers
(0x5328 and 0x532a) (See “2.4 Vector Table”). “TTBR” in Table 6.2.1 indicates the values set for these registers.
The MISC_TTBRL and MISC_TTBRH registers are set to the 0x8000 address after initial resetting. Table 6.2.1
shows the S1C17601 vector table.
Table 6.2.1: Vector table
Vector No./ Soft-
ware interrupt No.
Vector
address
Hardware interrupt name
Hardware interrupt factor
Priority
Mask
0 (0x00)
TTBR + 0x00 Reset
Low input to #RESET pin
Watchdog timer overflow 2
1
impos-
sible
1 (0x01)
TTBR + 0x04 Irregular address interrupt
Memory access instruction
2
–
(0xfffc00)
Debug interrupt
brk instruction etc.
3
2 (0x02)
TTBR + 0x08 NMI
Watchdog timer overflow 2
4
3 (0x03)
TTBR + 0x0c Compiler (reserved)
Use simulation library of C compiler
–
4 (0x04)
TTBR + 0x10 P0 port interrupt
P00 to P07 port input
High 1 Possible
5 (0x05)
TTBR + 0x14 P1 port interrupt
P10 to P17 port input
6 (0x06)
TTBR + 0x18 Stopwatch timer interrupt
Timer 100 Hz signal
Timer 10 Hz signal
Timer 1 Hz signal
7 (0x07)
TTBR + 0x1c Clock timer interrupt
Timer 32 Hz signal
Timer 8 Hz signal
Timer 2 Hz signal
Timer 1 Hz signal
8 (0x08)
TTBR + 0x20 8-bit OSC1 timer interrupt
Compare match
9 (0x09)
TTBR + 0x24 SVD interrupt
Power supply voltage drop detection
10 (0x0a)
TTBR + 0x28 LCD interrupt
Frame signal
11 (0x0b)
TTBR + 0x2c PWM timer Ch.0 interrupt
Compare A
Compare B
12 (0x0c)
TTBR + 0x30 8-bit timer interrupt
Timer underflow
13 (0x0d)
TTBR + 0x34 16-bit timer Ch.0 interrupt
Timer underflow
14 (0x0e)
TTBR + 0x38 16-bit timer Ch.1 interrupt
Timer underflow
15 (0x0f)
TTBR + 0x3c 16-bit timer Ch.2 interrupt
Timer underflow
16 (0x10)
TTBR + 0x40 UART interrupt
Transmit buffer empty
Receive buffer full
Receive error
17 (0x11)
TTBR + 0x44 I2C (slave) interrupt
I2C (slave) transmit buffer empty
I2C (slave) receive buffer full
I2C (slave) bus status change
18 (0x12)
TTBR + 0x48 SPI interrupt
Transmit buffer empty (only Master mode)
Receive buffer full
19 (0x13)
TTBR + 0x4c I2C (master) interrupt
Transmit buffer empty
Receive buffer full
20 (0x14)
TTBR + 0x50 PWM timer Ch.1 interrupt
Compare A
Compare B
21 (0x15)
TTBR + 0x54
reserved
–
22 (0x16)
TTBR + 0x58 A/D converter interrupt
Conversion finish
Conversion result override
23 (0x17)
TTBR + 0x5c R/F converter interrupt
Standard oscillation finish
Sensor A oscillation finish
Sensor B oscillation finish
Timebase counter override
Measurement counter override
24 (0x18)
TTBR + 0x60
reserved
–
:
31 (0x1f)
TTBR + 0x7c
reserved
–
Low 1
1: When same interrupt level is set
2: Watchdog timer interrupt selects reset or NMI using software.
Vector numbers 4 to 20, 22 to 23 are assigned maskable interrupts supported by the S1C17601.